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TMPR3911 Datasheet(PDF) 197 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 197 Page - Toshiba Semiconductor

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Chapter 7 CHI Module
7-23
7.4.6
CHI Transmit Pointer B Register
OFFSET
= $1EC:
write-only
Bit
Label
RESET
Read/Write
31-29
Reserved
28-24
CHITXPTRB3[4:0]
X
W
23-21
Reserved
20-16
CHITXPTRB2[4:0]
X
W
15-13
Reserved
12-8
CHITXPTRB1[4:0]
X
W
7-5
Reserved
4-0
CHITXPTRB0[4:0]
X
W
CHITXPTRB3[4:0]:
write-only
These bits represent the TDM switch pointer which defines the transmit channel timeslot for
byte 3 of the CHI transmit holding register B; register B handles all timeslots from channel
(CHINCHAN
+ 1) to channel (CHINCHAN × 2−1). The value loaded for this TDM switch pointer
is the desired timeslot number minus (CHINCHAN
+ 1).
CHITXPTRB2[4:0]:
write-only
These bits represent the TDM switch pointer which defines the transmit channel timeslot for
byte 2 of the CHI transmit holding register B; register B handles all timeslots from channel
(CHINCHAN
+ 1) to channel (CHINCHAN × 2−1). The value loaded for this TDM switch pointer
is the desired timeslot number minus (CHINCHAN
+ 1).
CHITXPTRB1[4:0]:
write-only
These bits represent the TDM switch pointer which defines the transmit channel timeslot for
byte 1 of the CHI transmit holding register B; register B handles all timeslots from channel
(CHINCHAN
+ 1) to channel (CHINCHAN × 2−1). The value loaded for this TDM switch pointer
is the desired timeslot number minus (CHINCHAN
+ 1).
CHITXPTRB0[4:0]:
write-only
These bits represent the TDM switch pointer which defines the transmit channel timeslot for
byte 0 of the CHI transmit holding register B; register B handles all timeslots from channel
(CHINCHAN
+ 1) to channel (CHINCHAN × 2−1). The value loaded for this TDM switch pointer
is the desired timeslot number minus (CHINCHAN
+ 1).



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