TMPR3911 datasheet(199/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-25

ENDMATXCHI:

This bit enables the CHI DMA transmit function. Setting this bit to a logic “1” enables the DMA

mode. Clearing this bit to a logic “0” disables the DMA mode. This bit should not be set until the

CHIRXSTART, CHITXSTART, and CHISIZE registers are setup. To enable CHI DMA transmit

function, this bit must be set before the CHI Module is enabled (ENCHI asserted). Either

ENDMARXCHI or ENDMATXCHI or both can be set at a time since the CHI DMA controller can

support full duplex operation.

7.4.8

CHI RX Start Register

OFFSET

= $1F4:

write-only

Bit

Label

RESET

Read/Write

31-2

CHIRXSTART[31:2]

1-0

Reserved

CHIRXSTART[31:2]:

write-only

These bits define the start address for the CHI RX DMA buffer. The CHI RX buffer and CHI TX

buffer can be configured to either reside in different memory spaces or share the same memory

space (overlapping buffers for loopback purposes or for optimum memory allocation).

7.4.9

CHI TX Start Register

OFFSET

= $1F8:

write-only

Bit

Label

RESET

Read/Write

31-2

CHITXSTART[31:2]

1-0

Reserved

CHITXSTART[31:2]:

write-only

These bits define the start address for the CHI TX DMA buffer. The CHI RX buffer and CHI TX

buffer can be configured to either reside in different memory spaces or share the same memory

space (overlapping buffers for loopback purposes or for optimum memory allocation).

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