TMPR3911 datasheet(198/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-24

7.4.7

CHI Size Register

OFFSET

= $1F0:

Bit

Label

RESET

Read/Write

31-30

Reserved

29-18

CHIDMAPTR[13:2]

–

17-16

Reserved

CHIBUFF1TIME

R/W

CHIDMALOOP

R/W

13-2

CHISIZE[13:2]

ENDMARXCHI

R/W

ENDMATXCHI

R/W

CHIDMAPTR[13:2]:

read-only

These bits provide the status of the CHI DMA counter.

CHIBUFF1TIME:

The CHI DMA controller supports two buffer addressing modes depending on the state of this

bit. When CHIBUFF1TIME is set to a logic “1”, the CHI DMA controller will stop executing

when it reaches the end of the DMA buffer. When CHIBUFF1TIME is cleared to a logic “0”, the

CHI DMA controller will loop back to the start of the DMA buffer when the end of the DMA

buffer is reached and will continue operating in a continuous and circular manner.

CHIDMALOOP:

The CHI DMA controller supports two full-duplex loopback modes depending on the state of

this bit. When CHIDMALOOP is set to a logic “1”, the CHI DMA controller issues RX DMA

requests first, followed by TX DMA requests. This ordering allows an RX-to-TX immediate

loopback via the DMA buffer. When CHIDMALOOP is cleared to a logic “0”, the CHI DMA

controller issues TX DMA requests first, followed by RX DMA requests. This ordering allows a

single circular DMA buffer to be used for both TX and RX, if so desired.

CHISIZE (13:2):

write-only

These bits define the size of the CHI DMA buffers (16 Kbytes maximum). Both the CHI RX

buffer and the CHI TX buffer are the same size. The last address in the CHI RX DMA buffer is

given by CHIRXSTART[31:2]

+ CHISIZE[13:2]. The last address in the CHI TX DMA buffer is

given by CHITXSTART[31:2]

+ CHISIZE[13:2]. The value loaded into CHISIZE should be equal

to the desired buffer length

−1.

ENDMARXCHI:

This bit enables the CHI DMA receive function. Setting this bit to a logic “1” enables the DMA

mode. Clearing this bit to a logic “0” disables the DMA mode. This bit should not be set until the

CHIRXSTART, CHITXSTART, and CHISIZE registers are setup. To enable CHI DMA receive

function, this bit must be set before the CHI Module is enabled (ENCHI asserted). Either

ENDMARXCHI or ENDMATXCHI or both can be set at a time since the CHI DMA controller can

support full duplex operation.

TMPR3911 Datasheet(PDF) 198 Page - Toshiba Semiconductor

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