TMPR3911 datasheet(203/462 Pages) TOSHIBA

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Chapter 8 Interrupt Module

8-3

8.2.2

Interrupt Logic Description

Figure 8.2.1 shows a block diagram of the interrupt circuit for a single interrupt source. Every other

interrupt source contains an identical circuit.

The overall Interrupt Module contains 5 main sets of registers (numbered 1 through 5), with a 6th

Priority Interrupt Vector and IRQHIGH and IRQLOW status bits. Each bit within each of the 5 main

sets then consists of 3 registers: Status, Enable, and Clear.

•

Interrupt Status Register

read-only

•

allows CPU to read logic state of interrupt status

•

informs the CPU which interrupts are pending

•

Enable Interrupt Register

read/write

•

allows CPU to enable a given interrupt

•

each individual interrupt has a corresponding enable bit

•

Clear Interrupt Register

write-only

•

allows CPU to clear a given pending interrupt

•

each individual interrupt has a corresponding clear bit

•

each individual interrupt clear address and bit position maps one-to-one with the interrupt

status address and bit position (status transactions are CPU reads, clear transactions are CPU

writes)

A given Interrupt Status Register is set by the corresponding individual interrupt event. For example,

this event could be a positive (or negative) edge transition on an external TMPR3911/12 pin. Another

example might be an event triggered by an internal TMPR3911/12 module, such as a particular DMA

buffer reaching the end-of-buffer point.

The output of a given Interrupt Status Register is readable by the CPU, by reading the address which

points to the corresponding Interrupt Status Register. A given interrupt is enabled by writing a “1” to the

corresponding bit position in the corresponding Enable Interrupt Register. The Interrupt Status Register

output bit is then gated with the enable bit from the corresponding Enable Interrupt Register. The output

of this gate is then combined with all the other gated Interrupt Status bits using a wide bitwise “OR”

tree in order to generate the IRQLOW status signal. In other words, if ANY of the gated Interrupt Status

signals is asserted and the global interrupt enable GLOBALEN is asserted, then IRQLOW will be

asserted.

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