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TMPR3911 Datasheet(PDF) 214 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 214 Page - Toshiba Semiconductor |
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214 / 462 page ![]() Chapter 8 Interrupt Module 8-14 SPIRCVINT: This interrupt is set whenever the contents of the SPI Shift Register are transferred to the SPI Receiver Holding Register. This interrupt is used to indicate that there is valid data in the SPI Receiver Holding Register to be read by the software. SPIEMPTYINT: This interrupt is set whenever the both the SPI Shift Register and the SPI Transmitter Holding Register are empty. This interrupt can be used by the software to determine when the SPI is idle. IRCONSMINT: Whenever the upper byte of data is loaded into the 7-bit Period Number Counter, the lower byte of data is loaded into an intermediate holding register. At this time the 16-bit IR Holding Register is empty. The IRCONSMINT interrupt is then set to inform the CPU that the IR Holding Register is available. The CPU must fill the next word of data into the IR Holding Register before the 7-bit Period Number Counter is finished counting the periods for both the upper and lower bytes of data. CARSTINT: This interrupt is set whenever the Carrier Detect State Machine detects the CARDET pin is high just before turning off the RXPWR pin. POSCARINT: This interrupt is set whenever CARDET pin transitions from a logic “0” to a logic “1”. NEGCARINT: This interrupt is set whenever CARDET pin transitions from a logic “1” to a logic “0”. IOPOSINT (6:0): Issues an interrupt whenever any of the general purpose I/O pin(s) transitions from a logic “0” to a logic “1”. There are a total of 7 general purpose I/O pins (6 thru 0), each of which corresponds to the respective bit within this Status Register. Each general purpose I/O pin can independently trigger an interrupt. IONEGINT (6:0): Issues an interrupt whenever any of the general purpose I/O pin(s) transitions from a logic “1” to a logic “0”. There are a total of 7 general purpose I/O pins (6 thru 0), each of which corresponds to the respective bit within this Status Register. Each general purpose I/O pin can independently trigger an interrupt. |
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