TMPR3911 datasheet(215/462 Pages) TOSHIBA

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Chapter 8 Interrupt Module

8-15

8.3.6

Interrupt Status 6 Register

OFFSET

= $114:

read-only

Bit

Label

RESET

Read/Write

IRQHIGH

–

IRQLOW

–

PWROKNMI

R/W

28-6

Reserved

5-2

INTVECT[3:0]

–

1-0

Reserved

IRQHIGH:

This status bit is the bitwise “OR” of all the 16 possible high priority interrupts.

IRQLOW:

This status bit is the bitwise “OR” of all the interrupts contained in the Interrupt Status 1, 2, 3, 4,

and 5 Registers.

PWROKNMI:

When this bit is set, input to the PWROK pin can be used as the NMI source for the TX39/H

core. When the bit is cleared, NMI for the TX39/H core is disabled.

INTVECT[3:0]:

These 4 status bits indicate a vector pointing to the highest priority pending interrupt from the

set of 16 possible high priority interrupt events. The set of high priority interrupts is listed below,

where level 15 is the highest priority and level 1 is the lowest priority. Level 0 corresponds to the

standard interrupt handler.

priority level

high priority interrupt source

POSPWROKINT or NEGPWROKINT

ALARMINT

PERINT

MBUSPOSINT or MBUSNEGINT

UARTARXINT

UARTBRXINT

MFIOPOSINT (19) or MFIOPOSINT (18) or

MFIOPOSINT (17) or MFIOPOSINT (16)

MFIOPOSINT (1) or MFIOPOSINT (0) or

IOPOSINT (6) or IOPOSINT (5)

MFIONEGINT (19) or MFIONEGINT (18) or

MFIONEGINT (17) or MFIONEGINT (16)

MFIONEGINT (1) or MFIONEGINT (0) or

IONEGINT (6) or IONEGINT (5)

MBUSDMAFULLINT

SNDDMACNTINT

3TELDMACNTINT

CHIDMACNTINT

IOPOSINT (0) or IONEGINT (0)

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