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TMPR3911 Datasheet(PDF) 276 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 276 Page - Toshiba Semiconductor

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Chapter 13 SIB Module
13-6
13.3 Interface Requirements
13.3.1
Frame Structure
Each SIB frame consists of 128 SIBSCLK, further divided into 2 subframes: Subframe 0 and 1. The
SIB frame structure is shown in Figure 13.3.1.
Subframe 0
Subframe 1
1 Frame
SIBSYNC
SIBSCLK
SIBDIN
SIBDOUT
Figure 13.3.1 SIB Framing Structure
13.3.2
Timing Requirements
The TMPR3911/12 always samples receive data (SIBDIN) on the falling edge of SIBSCLK, whereas
the transmit data from TC35143 is always output on the rising edge of SIBSCLK. Similarly, the
TMPR3911/12 always output transmit data (SIBDOUT) on the rising edge of SIBSCLK, whereas the
transmit data to TC35143 is always sampled on the falling edge of SIBSCLK in TC35143.
The SIBSYNC signal is asserted for one SIBCLK cycle immediately before each frame starts and all
devices connected to the SIB monitor SIBSYNC to determine when they should transmit or receive
data. SIBSYNC is always sampled by TC35143 on the falling edge of SIBSCLK. The timing
relationship for the SIBSCLK, SIBSYNC, and data signals (SIBDIN, SIBDOUT) is shown in Figure
13.3.2.
2
1
63
Subframe 1 start
Frame start
SIBDOUT
SIBDIN
SIBSYNC
SIBSCLK
Subframe 0
062
63
0
Subframe 1
Figure 13.3.2 SIB Timing Relationships



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