TMPR3911 datasheet(277/462 Pages) TOSHIBA

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Chapter 13 SIB Module

13-7

13.3.3

Configurations

Many configuration options exist for the SIB. The SIB Module control bits SELSNDSF1 and

SELTELSF1 are used to determine the desired SIB configuration. See Table 13.3.1 for a summary

matrix of these possible configurations. The lowest cost configuration utilizes TC35143 only, assigned

to subframe 0 of the SIB, while subframe 1 is not used. For this configuration, the system utilizes the

audio and telecom codecs within TC35143. The SIBSCLK rate is fixed and the independent sound and

telecom sample rates are controlled via TMPR3911/12 and TC35143 programmable counters.

Table 13.3.1 SIB Configuration Matrix (1)

TMPR3912AU-92/XB-92; 11.520 MHz crystal to be used. RF[1:0] = 00, SLOWBUS = 0.

sound

codec

telecom

codec

TMPR3912

clk2x [1]

sibsclk

sibmclk out

or sound

OSC in [2]

SIB

frame

rate [3]

comments

TC35143;

= 8K,

11.05K, 16K,

or 22.15K

TC35143;

= 7.2K,

8K, or 9.6K

92.16M

9.216M

(

÷10)

18.432M

out (

÷5)

72K

TC35143 only;

lowest cost;

sibsclk

= fixed;

sound & telecom Fs control;

via TC35143 prgm [4];

SIB subframe0

= TC35143;

SIB subframe1

= not used;

SELSNDSF1

= 0;

SELTELSF1

= 0;

Table 13.3.2 SIB Configuration Matrix (2)

The TMPR3911BU/BXB SIB does not provide support for a 7.3728-MHz crystal. To use the SIB,

use a 6.912-MHz crystal. RF[1:0]=00, SLOWBUS=0.

sound

codec

telecom

codec

TMPR3912

clk2x [1]

sibsclk

sibmclk out

or sound

OSC in [2]

SIB

frame

rate[3]

comments

TC35143;

= 8 k

11.05 k, 16 k,

or 22.15 k

TC35143;

= 7.2 k,

8 k, or 9.6 k

55.296 M

9.216 M

(

÷6)

18.432 M

out (

÷3)

72 k

TC35143 only;

lowest cost;

sibsclk

= fixed;

sound & telecom Fs control;

via TC35143 prgm [4];

SIB subframe1

= not used;

SELSNDSF1

= 0;

SELTELSF1

= 0;

NOTES :

[1]

TMPR3911/12 clk2x is internal high-rate system-wide clock

[2]

optional external sound OSC can be connected to TMPR3911/12 sibmclk (to allow decoupling of

SIB clocks from clk2x; else this pin can be configured as buffered sibmclk output which is

synchronously divided down from clk2x (sibmclk allows potential support of codecs requiring a

high-rate fixed master clock

+ a sample-rate-dependent serial clock); sibsclk serial clock is always

synchronously divided down from sibmclk

[3]

SIB frame rate

= sibsclk ÷ 128; ratio for average number of SIB-frames per valid-data-frame is

dependent upon sound & telecom Fs

[4]

TC35143 audio/telecom Fs divider programmability: SIB-frame/valid-data-frame RATIO

(sibsclk

× 2) ÷ (40 × 64) = 7.2K

(sibsclk

× 2) ÷ (36 × 64) = 8K

4.5

(sibsclk

× 2) ÷ (30 × 64) = 9.6K

3.75

(sibsclk

× 2) ÷ (15 × 64) = 19.2K (1.6% error vs. 18.9K for CD-XA)

1.875

(sibsclk

× 2) ÷ (13 × 64) = 22.154K (0.47% error vs. 22.050K for CD-Audio)

1.625

(sibsclk

× 2) ÷ (12 × 64) = 24K

1.5

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