TMPR3911 datasheet(274/462 Pages) TOSHIBA

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Chapter 13 SIB Module

13-4

13.2.1

Holding and Shift Registers

The SIB Module logic consists of holding registers (both transmit and receive) and a serial shift

TMPR3911/12 and TC35143 (and/or other external codec devices) via the SIB (see Figure 13.2.1 for a

block diagram of the SIB Module).

For the SIB transmit direction, the sound and telecom transmit holding registers are written either

from the DMA circuit or directly from the CPU, while the subframe 0 and subframe 1 control holding

registers are always written directly from the CPU. These holding registers are processed by an array of

multiplexers which select which fields of the various 32-bit transmit holding registers are loaded into

the 64-bit shift register, such that an entire subframe is loaded in parallel and then shifted out the serial

output SIBDOUT. The sequence of loading the shift register from the various holding register fields is

determined by the programmed sound and telecom sample rates, mono versus stereo mode, and 8-bit

versus 16-bit modes.

Conversely, for the SIB receive direction, the sound and telecom receive holding registers are read

either by the DMA circuit or directly by the CPU, while the subframe 0 and subframe 1 status holding

registers are always read directly by the CPU. The 64-bit shift register containing an entire subframe of

received data from the serial input SIBDIN is processed by an array of multiplexers which select which

fields of the various 32-bit receive holding registers are loaded from the shift register. The sequence of

loading the various fields of the receive holding registers from the shift register is determined by the

programmed sound and telecom sample rates, mono versus stereo mode, left versus right mono source,

and 8-bit versus 16-bit modes.

13.2.2

Clock and Sync Generation

The SIB Module logic contains several programmable counters which are used to generate the

various SIB internal and external control signals and clocks. See Figure 13.2.2 for a block diagram of

the SIB clock and sync generation circuit. As mentioned previously, SIBMCLK can be configured as

either an input or output. As an output, SIBMCLK is derived by dividing down from CLK2X. In this

mode, all SIB clocks are then synchronously slaved to the main TMPR3911/12 system clock and only

one main XTAL source is required for the entire system (besides the 32 kHz RTC XTAL), resulting in

the lowest cost system configuration with regards to clock sources. As an input, SIBMCLK is generated

from an external oscillator source, which is asynchronous with respect to CLK2X. This more expensive

configuration allows the SIB (and also potentially the CHI and dual-UART circuits) to operate

independent of the frequency used for the CPU core. This allows flexible system design options with

respect to the CPU operating frequency, along with the ability to generate the required or desired UART

baud rates and audio/telecom sampling frequencies.

The programmable SIBSCLK rate is derived by dividing down from SIBMCLK. Nominal rates for a

TC35143-only configuration are CLK2X

÷ 5 (TMPR3912AU-92/XB-92) and SIBSCLK = 9.216 MHz

(equals SIBMCLK

÷ 2). The SIBSCLK rate is then used to enable a set of counters (word counter and

subframe/frame counter) to generate the SIBSYNC frame rate of 72 kHz (equals SIBSCLK

÷ 128), as

well as various internal SIB clocks and control signals.

The subframe rate is used to enable independent sets of programmable sound and telecom sample

rate counters which generate various control signals based on the desired sample rates. For instance, this

logic correctly generates the sound and telecom valid flag bits which are asserted within the SIBDOUT

serial output stream every time a valid sample is being transmitted.

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