TMPR3911 datasheet(270/462 Pages) TOSHIBA

270 / 462 page

Chapter 12 Power Module

12-14

DBNCONBUTN:

If this bit is set, then the POSONBUTNINT and NEGONBUTNINT interrupts and the

ONBUTN wake up function will only occur after a minimum of 16 ms and a maximum of 24 ms

of debouncing of the ONBUTN signal has taken place to allow direct “undebounced” button

connection. If this bit is cleared, then the interrupts and power up occur immediately upon

transition of the ONBUTN signal.

COLDSTART:

This bit is set by RESET and provides status to the processor that a Power On Reset has

occurred.

PWRCS:

This bit is set whenever the ONBUTN signal is asserted or an enabled interrupt occurs while the

PWROK signal is high. When powering down the system, this bit must be cleared simultaneously

with the VCCON bit. All enabled interrupts must be cleared prior to powering down the system, or

the PWRCS and VCCON signals will not go low.

VCCON:

This bit is set whenever the ONBUTN is pressed or an enabled interrupt occurs if the PWROK

signal is high. When powering down the system, this bit must be cleared simultaneously with the

PWRCS bit. All enabled interrupts must be cleared prior to powering down the system, or the

PWRCS and VCCON signals will not go low.

TMPR3911 Datasheet(PDF) 270 Page - Toshiba Semiconductor