TMPR3911 datasheet(266/462 Pages) TOSHIBA

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Chapter 12 Power Module

12-10

12.2.6

Forced Shutdown

The Power Module provides a feature called Forced Shutdown that will force the system to power down

automatically if the PWROK signal goes low before the software clears the FORCESHUTDWN bit. The

main purpose of this feature is to protect the contents of DRAM or SDRAM. The timing sequence for

Forced Shutdown is shown in Figure 12.2.4. This feature can be enabled or disabled by setting the

ENFORCESHUTDWN bit in the Power Control Register. This feature is useful if a particular battery

provides a PWROK indication when there is no load on the battery, but quickly deasserts the PWROK signal

once the battery has some load by asserting VCC3. When this feature is disabled, the system will continue

the instruction execution and enable the persistent memory even if the PWROK signal is deasserted, and will

eventually stop by the power failure and lose the data in the memory.

The FORCESHUTDWN bit is set whenever PWRCS is asserted as a result of the ONBUTN being pressed

or an enabled interrupt being set when the device is off. If the PWROK signal goes low prior to the software

clearing the FORCESHUTDWN bit, the Power Module will simply deassert the PWRCS signal and the

System Power Supply will turn off the VCC3 power supply.

The instruction to clear the FORCESHUTDWN bit must be executed prior to bringing the memory

interface out of self-refresh mode. This implies that the instruction has to be pre-loaded into the cache before

the previous system shutdown, since the memory interface will exit self refresh mode once an address

location is accessed in the system that is not in the cache or not to a function register. The very first time that

the system is turned on after the assertion of VSTANDBY, it is not possible to support this function since the

cache is not initialized. This is not a problem because the main purpose of this feature is to protect the

contents of DRAM or SDRAM, which does not exist when the device is turned on for the first time.

PWRCS (out)

FORCESHUTDWN bit

VCC3 (in)

PWROK (in)

ONBUTN (in)

Figure 12.2.4 Forced Shutdown Sequence

12.2.7

Memory Power Down

By setting the MEMPOWERDOWN bit in the Memory Configuration 4 Register, the memory

controller goes into Memory Power Down Mode. All memory signals will be driven low and DRAMs

and/or SDRAMs will go into self-refresh mode. The software can only access to the cache memory and

the internal function registers. The first access outside them clears the MEMPOWERDOWN bit and

DRAMs and/or SDRAMs will go out of the self-refresh mode. Thus it is necessary that all instructions

following the assertion of the MEMPOWERDOWN bit need to be executed on the cache memories.

12.2.8

Stop Timer

The Stop Timer is used as a coarse timer to bring the CPU out of Stop Mode. The Stop Timer consists

of a 4-bit up counter and a comparator to generate the STPTIMERINT interrupt. The Stop Timer is

enabled using the ENSTPTIMER control bit in the Power Control Register. When the ENSTPTIMER

control bit is not set the counter will be reset to zero. Once the ENSTPTIMER bit is set the counter will

count up using an 8 ms clock as the input. Once the counter reaches a value that is equal to the

STPTIMERVAL[3:0] control bits, the STPTIMERINT interrupt is set. The Stop Timer will provide a

maximum duration of 120 ms, in steps of 8 ms.

TMPR3911 Datasheet(PDF) 266 Page - Toshiba Semiconductor

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