TMPR3911 datasheet(264/462 Pages) TOSHIBA

264 / 462 page

Chapter 12 Power Module

12-8

12.2.4

Power Up

When the system is off if rising edge of the ONBUTN signal or an enabled interrupt occurs, and the

PWROK signal is asserted, then the system will power up. If assertion of the ONBUTN signal or an

enabled interrupt occurs, but the PWROK signal is deasserted, then the system will not power up at that

time. But since the interrupt is latched, the system will power up once the PWROK signal is asserted.

On the other hand, the assertion of the ONBUTN signal is not a latched event unless the

POSONBUTNINT or NEGONBUTNINT interrupts are enabled. Therefore, the assertion of the

ONBUTN signal will not wake up the system once PWROK signal is asserted.

Once the ENSYSCLK (internal signal) goes low, the clock to the CPU is stopped and the CPU will

remain suspended at its last state. When the device powers back up, the ENSYSCLK will be asserted

16-24 ms after VCC3 is asserted or 4-6 ms after VCC3 is asserted, depending on the state of the

SELC2MS control bit in the Power Control Register. Then the CPU will resume the instruction

execution from where it stopped. It is probably desirable to loop for some time to make sure that the

battery voltage has stabilized and the PWROK signal will not suddenly go low as a result of a

substantial load added to the battery. Once the loop has completed, the software must clear the

FORCESHUTDWN bit prior to accessing any address that is not in the cache or the internal function

registers (See Section 12.2.6).

PWROK (in)

ONBUTN (in)

PWRCS (out)

ENSYSCLK (internal)

DCLKOUT (out)

(MEMPOWERDOWN: by software)

(PWRCS/VCCON: by software)

Interrupt

Delayed Interrupt

Power Down

Power Up

by delayed interrupt

16-24 ms

or 4-6ms

VCC3 (in)

Figure 12.2.3 Power Down and Power Up Sequence

TMPR3911 Datasheet(PDF) 264 Page - Toshiba Semiconductor