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TMPR3911 Datasheet(PDF) 263 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 263 Page - Toshiba Semiconductor

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Chapter 12 Power Module
12-7
12.2.3
Power Down
A state transition into the Suspend State is called ‘Power Down’. Typically this is triggered by assertion
of the ONBUTN signal to power off the system. In the Suspend State VSTANDBY and VCCDRAM are
powered but VCC3 is not powered. Some system may have some other power supply lines which are
powered during the Suspend State. For example a system may supply power to a PC Card during the
Suspend State.
If the system is powered up and the PWROK signal is deasserted, the system must be powered down as
quickly as possible to preserve the contents of DRAM and/or SDRAM. All power supply lines, which are
not required to preserve valuable data, must be powered off. This state is called the Battery Backup State.
The system is powered down by software in the following sequence.
1.
All modules in the TMPR3911/12 are disabled and all clocks in the Clock Module are turned
off.
2.
The interrupts for the wake-up events such as power switch, alarm (RTC), and serial DCD are
enabled, and the other interrupts are disabled.
When the PWROK signal is deasserted, some system may disable all interrupts to prevent
unexpected power up after power will be supplied again.
3.
The MEMPOWERDOWN bit in the Memory Configuration 4 Register is set in order to set the
DRAM and/or SDRAM into self-refresh mode. The following instructions must be executed
from cache memory. See Section 0 for more details.
4.
By clearing the PWRCS and VCCON bits in the Power Control Register simultaneously the
PWRCS signal is deasserted. After the PWRCS is deasserted, the System Power Supply shuts
down VCC3 power line. Clearing VCCON bit results in negating ENSYSCLK and stopping all
internal clocks except 32kHz clock.
A wait loop for a few milliseconds follows. A few instructions may be executed before power off. The
rest of the wait loop is executed after the next power up to guarantee that some devices in the system are
stable after power up.



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