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TMPR3911 Datasheet(PDF) 261 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 261 Page - Toshiba Semiconductor |
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261 / 462 page ![]() Chapter 12 Power Module 12-5 12.2 Description 12.2.1 Power On Reset When VSTANDBY is powered on, the PON* signal must be kept low until VSTANDBY is stable, in order to provide a good Power On Reset to the TMPR3911/12. The assertion of PON* will set a RESET flip-flop, as shown in Figure 12.2.1. The RESET flip-flop will remain set until the ONBUTN is pressed for the first time. This functionality provides a long reset time to the TMPR3911/12 when VSTANDBY is first asserted. The long reset time is needed to allow the 32 kHz oscillator to stabilize. The RESET signal is used to initialize all registers and logic in the TMPR3911/12. Figure 12.2.1 Reset Flip-Flop ONBUTN PON* RESET |
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