TMPR3911 datasheet(262/462 Pages) TOSHIBA

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Chapter 12 Power Module

12-6

12.2.2

The 1

st Power Up

The 1

st Power Up sequence is shown in Figure 12.2.2 When the ONBUTN is pressed, the PWRCS

signal will be asserted if the PWROK signal is high. Once the PWRCS signal is asserted, the System

Power Supply powers VCCDRAM and VCC3 in order to power up the system. Once VCC3 is powered,

the high frequency oscillator and PLL that generate the clock signals for the CPU and BIU start

clocking. When the oscillator and PLL are first enabled, the oscillation can vary widely until the

oscillator and PLL become stable. The stabilization time can vary between 1 ms and 10 ms, depending

on the oscillator and PLL of a particular TMPR3911/12 implementation. In order to prevent the

TMPR3911/12 from using the clock before the clock becomes stable, a circuit in the Power Module will

provide an internal signal ENSYSCLK that will disable the clock until the oscillator and PLL become

stable. The circuit uses the 32 kHz signal as its reference, since this is known to be good because of the

long Power On Reset time. The ENSYSCLK is asserted 16-24 ms after VCC3 is asserted at the 1

power up. Once the ENSYSCLK signal is asserted, the CPU will start instruction execution.

If the PWROK signal is low when the ONBUTN is pressed, the PWRCS signal will not be asserted.

The “PON* state” and the “1

st-time power-up state” in the Figure 12.2.2 are defined on page 2-17.

C32K Oscillator Stabilization Time

min.1-2 s

Voltage Stabilization Time

RESET (internal)

VCC3 (in)

VSTANDBY (system)

PON* (in)

PWROK (in)

ONBUTN (in)

PWRCS (out)

16-24 ms

DCLKOUT (out)

ENSYSCLK (internal)

Instruction Execution

st Time Power-up State

PON* state

pin state

Figure 12.2.2 The 1

st Power Up Sequence

TMPR3911 Datasheet(PDF) 262 Page - Toshiba Semiconductor