| Electronic Components Datasheet Search |
|
TMPR3911 Datasheet(PDF) 265 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMPR3911 Datasheet(HTML) 265 Page - Toshiba Semiconductor |
|
265 / 462 page ![]() Chapter 12 Power Module 12-9 12.2.5 Stop CPU In order to reduce the power consumption in the TMPR3911/12, it is desirable to stop the clock to the CPU when the CPU does not have to execute instructions. This is possible since the CPU core is fully static and will simply resume the instruction execution from where it stopped when the clock is re-enabled. The states in which just the CPU clock stops are called the Standby State or the Idle State. The system goes into the Standby State by software in the following sequence. The IEc bit in the Status Register of the CPU core is cleared to disable interrupt. 1. The software may change RF bits in the Config Register of the CPU core and SLOWBUS bit in the Power Control Register to reduce clock frequencies of DCLKOUT, CORECLK, CLK2X, and CLK (See Section 6.2.1) for power saving. The reduced frequency must be determined to maintain the system activity (DMA, peripheral device operation, etc.) in the Standby State. 2. The software can stop the clock to the CPU by setting the STOPCPU bit in the Power Control Register. Once this bit is set, the clock to the CPU will be stopped and remains stopped until an enabled interrupt clears the STOPCPU bit. This bit should not be set when powering down the system because the ENSYSCLK signal is a more dominant clock shutdown signal for the entire TMPR3911/12 chip. 3. A program loop waiting for the STOPCPU bit to be set follows. Some instructions are executed, then the CPU core stops. When any enabled interrupt events occur the system goes back to the Normal State promptly. The following software sequence should be done. 1. The CPU core restarts the execution of the program loop waiting for the STOPCPU bit to be cleared and exits from the loop promptly since the STOPCPU bit is cleared. 2. Resume the value of the RF bits and SLOWBUS bit. 3. The IEc bit in the Status Register of the CPU core is set to enable interrupt. 4. The CPU core jumps to the interrupt handler for the interrupt that waked up the system. The IEc bit is used to resume the RF bits and SLOWBUS bit before jumping to the interrupt handler. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |