TMPR3911 datasheet(268/462 Pages) TOSHIBA

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Chapter 12 Power Module

12-12

12.3 Power Registers

12.3.1

Power Control Register

OFFSET

= $ 1C4:

Bit

Label

RESET

Read/Write

ONBUTN

–

PWRINT

–

PWROK

–

28-27

VIDRF[1:0]

R/W

SLOWBUS

R/W

DIVMOD

R/W

24-16

Reserved

15-12

STPTIMERVAL[3:0]

R/W

ENSTPTIMER

R/W

ENFORCESHUTDWN

R/W

FORCESHUTDWN

R/W

FORCESHUTDWNOCC

R/W

7SELC2MS

R/W

Reserved

BPDBVCC3

R/W

4STOPCPU

R/W

DBNCONBUTN

R/W

2COLDSTART

R/W

1PWRCS

R/W

VCCON

R/W

ONBUTN:

read-only

This bit provides the status of the ONBUTN signal.

PWRINT:

read-only

This bit provides the status of the PWRINT signal.

PWROK:

read-only

This bit provides the status of the PWROK signal.

STPTIMERVAL[3:0]:

When the Stop Timer is enabled the STPTIMERINT interrupt will be set when the counter is

equal to the value set by these bits.

ENSTPTIMER:

This bit is used to enable the Stop Timer.

VIDRF[1:0]:

These bits select the divide-ratio of VIDCLK, which is the master clock used for the video

module.

VIDRF

divide-ratio

TMPR3911 Datasheet(PDF) 268 Page - Toshiba Semiconductor

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