TMPR3911 datasheet(269/462 Pages) TOSHIBA

269 / 462 page

Chapter 12 Power Module

12-13

SLOWBUS:

Setting this bit will cause the internal clocks except FREECLK and XHFEE to be divided by 2.

DIVMOD:

Setting this bit will cause the clocks in each function module such as an UART to be

independent of RF (1:0). (See Section 6, Figure 6.2.1 and 6.2.2)

ENFORCESHUTDWN:

The FORCESHUTDWN bit is set whenever the VCCON bit and the PWRCS bit are set by

either the ONBUTN signal assertion or an enabled interrupt occurrence. If the PWROK signal goes

low before the processor clears the FORCESHUTDWN bit, then the VCCON bit and the PWRCS

bit are cleared and the PWRCS signal will go low if the ENFORCESHUTDWN bit is set. If the

ENFORCESHUTDWN bit is not set, then the FORCESHUTDWN bit will have no effect.

FORCESHUTDWN:

If the ENFORCESHUTDWN bit is set, then this bit must be cleared after the initial boot, but

prior to memory interface waking up procedure. See Section 12.2.6 for details.

FORCESHUTDWNOCC:

This bit is set if a Forced Shutdown occurs due to the PWROK signal going low prior to the

processor clearing the FORCESHUTDWN bit. This bit provides status to the processor to indicate

that the event occurred. The bit should be cleared once the status has been checked, so that it can

be used again for the next power up.

SELC2MS:

The assertion of PWRCS signal will cause the System Power Supply to assert the VCC3 power

line. Once VCC3 is powered, the oscillator and PLL inside of the TMPR3911/12 will wake up and

generate the main system clock, but for a certain period of time the clock will be unstable until the

oscillator and PLL lock on the correct frequency. The Power Module will prevent the clock from

driving any logic until the clock becomes stable. The reference clock for the debouncing delay time

is provided by the C2MS (2 ms clock) and the C8MS (8 ms clock) internal signals generated by the

RTC from the 32 kHz oscillator. If SELC2MS is set to a logic “1”, the clock will be disabled for a

minimum of 4 ms and a maximum of 6 ms after VCC3 is powered. If SELC2MS is set to a logic

“0”, the clock will be deasserted for a minimum of 16 ms and a maximum of 24 ms after VCC3 is

powered.

BPDBVCC3:

If this bit is set, the clock will be enabled immediately following the assertion of VCC3, instead

of waiting for the delay mentioned in the SELC2MS bit description.

STOPCPU:

Setting this bit will cause the clock to the CPU core to be disabled to allow low power operation.

The bit is cleared whenever an enabled interrupt is set. This bit should not be set when powering

down the system. It is only used when the system is powered up, but the CPU does not have to

execute instructions.

TMPR3911 Datasheet(PDF) 269 Page - Toshiba Semiconductor