TMPR3911 datasheet(280/462 Pages) TOSHIBA

280 / 462 page

Chapter 13 SIB Module

13-10

13.3.5

Enable/Disable Sequencing

As mentioned in the previous section, the synchronization of the sample rate counters within

TMPR3911/12 and TC35143 is triggered from the codec enable command transmitted by

TMPR3911/12 and received by TC35143. The following steps illustrate the full sequence of events

needed to enable and disable the audio and/or telecom processing paths, while ensuring synchronization

of these sample rate counters (the example below shows a configuration with TC35143 for sound and

telecom, using subframe 0 only):

INITIAL ENABLE SEQUENCE:

(1) SIB is initially disabled (ENSIB

= 0)

(2) setup SIB control registers to desired settings (SIB clock rates, sample rate dividers, data formats

(8-bit vs. 16-bit, etc.), DMA settings, subframe 0 enable

= ENSF0

(3) write initial data and control values to transmit holding registers (SNDTXHOLD, TELTXHOLD,

SF0AUX); SF0AUX control register sets up TC35143 audio and telecom codecs, including sample

rate dividers (to match TMPR3911/12 sample rates), gains, etc. codecs are not enabled at this point

(4) enable SIB (assert ENSIB

= 1)

(5) SIB then begins transmitting and receiving data; TC35143 control registers get configured with

desired settings; codecs still not enabled at this point

SND (or TEL) ENABLE SEQUENCE:

(6) setup software to trigger from SIBSF0INT

(7) immediately after SIBSF0INT trigger, software must write to SF0AUX to assert Audio (or

Telecom) Codec Enable, and during same subframe (i.e., before SIBSF1INT event occurs),

software must assert ENSND (or ENTEL)

(8) after next SIBSF0INT and during the subframe 0 period, the Codec Enable Command is

transmitted from TMPR3911/12 and received by TC35143

(9) the Audio (or Telecom) Codec within TC35143 is then enabled at the start of the next frame after

the Enable Command is sent, at which time the sample rate counters within both TMPR3911/12

and TC35143 begin counting in a synchronized fashion

(10) during this first frame after codec is enabled, the first DAC sample is transmitted by

TMPR3911/12 (received by TC35143) and/or the first ADC sample is transmitted by TC35143

(received by TMPR3911/12); DAC and ADC samples are always transmitted during the same

subframe in a full-duplex manner (as mentioned in the previous section, DAC and ADC samples

are synchronized from the periodic sample rate counter rollover to the next available SIB

subframe)

(11) check valid status from TC35143 (indicates whether ADC’s are settled, all turn-on delays have

been met, etc.) which indicates valid samples

SND (or TEL) DISABLE SEQUENCE:

(12) software writes to SF0AUX to de-assert Audio (or Telecom) Codec Enable, in order to disable

codec

(13) software then de-asserts ENSND (or ENTEL) to disable sound (or telecom) processing on

TMPR3911/12 side

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