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TMPR3911 Datasheet(PDF) 282 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 282 Page - Toshiba Semiconductor

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Chapter 13 SIB Module
13-12
The SF0AUX control holding register and SF0STAT status holding register map directly to bits 16-31
and 48-63 of the subframe 0 word format. See Table 13.3.3 which shows the mapping of SF0AUX and
SF0STAT bit positions to the respective TC35143 fields. For TC35143, the audio and telecom “vflag”
bits (valid flags) in the transmit direction are dynamically asserted to TC35143 for one subframe each
time a new sample is being transmitted. The audio and telecom “vflag” bits in the receive direction are
statically asserted from TC35143 to the TMPR3911/12 only after the ADC’s are settled, all turn-on
delays have been met, etc. The TMPR3911/12 then uses these valid flags to determine when the receive
data from TC35143 is truly valid.
Table 13.3.3 SIB Subframe 0 Control/Status Bits and Fields
SF0AUX/SF0STAT
bits
TC35143 word bits
field definition
- - -
0-15
audio data
31
16
reserved for register extension; must write to 0 if not
used
30-27
17-20
register address[3:0]
26
21
write bit
25-18
22-29
reserved, must write to 0
17
30
audio valid flag
16
31
telecom valid flag
- - -
32-47
telecom data
15-0
48-63
register data[15:0]
The last 16 bits of the TC35143 word is made up of control register data. The exact contents and
definition of this field is defined by the register address field and the “write” bit. For a read cycle
(“write” bit
= 0), the address bits determine which TC35143 register to read and this read data is sent by
TC35143 within the control register data field of SIBDIN during the same frame as the read request
occurred. The separation between the address and data fields should make this possible. In addition,
during a read cycle, the control register data field of SIBDOUT is ignored by TC35143. For a write
cycle (“write” bit
= 1), the control register data contents of SIBDOUT are written to the TC35143
register pointed to by the register address field.
13.3.7
Subframe Formats
SIB subframe 0 is nominally reserved for interfacing to TC35143. Four possible sample-size modes
are supported for sound and telecom data (these are all mono sound and telecom formats):
sound
telecom
16-bit
16-bit
16-bit
8-bit
8-bit
16-bit
8-bit
8-bit
SIB subframe 1 is nominally reserved for interfacing to an external codec device.
For the external codec device, four possible sample-size modes are supported:
sound
telecom
16-bit stereo
16-bit
16-bit mono
8-bit
8-bit stereo
8-bit mono



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