TMPR3911 datasheet(285/462 Pages) TOSHIBA

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Chapter 13 SIB Module

13-15

13.4

DMA Address Generation

The SIB Module provides support for four independent DMA channels: sound receive and transmit

and telecom receive and transmit. Two identical circuits (one for sound DMA and one for telecom

DMA) are used to generate the DMA address, as well as half-buffer and end-of-buffer interrupts (see

Figure 13.4.1).

The DMA buffer size is programmable (up to a maximum of 16 Kbytes) and the receive and transmit

buffer start addresses are also programmable (anywhere over the full 32-bit address space). Because

there are separate start addresses, the receive and transmit buffers can be configured to either reside in

different memory spaces or share the same memory space. The latter setup allows for overlapping

buffers for loopback purposes or for optimum memory allocation, for which the DMA logic supports

two full-duplex loopback modes. For one mode, receive DMA requests are issued first, followed by

transmit DMA requests. This ordering allows a receive-to-transmit immediate loopback via the DMA

buffer. For the second mode, transmit DMA requests are issued first, followed by receive DMA

requests. Thus, received samples are written to the DMA buffer location immediately after transmit

samples were read from that same location (which then became immediately available). This ordering

allows a single circular DMA buffer to be used for both transmit and receive samples.

The DMA buffers can be configured in a circular buffer mode or a one-time buffer mode. For the

circular mode, the DMA address is continuously incremented (each time a DMA acknowledge is

received from the TMPR3911/12’s central DMA controller) and rolls over back to the start address after

the end-of-buffer is reached and will continue operating in a continuous and circular manner. For the

one-time mode, the DMA logic will stop executing whenever the end-of-buffer is reached.

Half-buffer and end-of-buffer DMA address counter interrupts are available, allowing the CPU to

minimize overhead and utilize the DMA buffer in a ping-pong fashion. For transmit mode, the CPU can

use these interrupts to fill or write one half of the buffer while the other half is being emptied by the

DMA controller for transmitting out the SIB. Similarly, for receive mode, the CPU can use these

interrupts to empty or read one half of the buffer while the other half is being filled by the DMA

controller from received SIB input samples.

Also available is a direct CPU read/write mode for bypassing the DMA, allowing the CPU to read or

write the sound or telecom data on a sample by sample basis, if so desired. Separate DMA enables for

receive and transmit allow DMA to be setup for receive only (transmit via CPU), transmit only (receive

via CPU), receive and transmit, or none (receive and transmit via CPU).

The sound and telecom DMA circuits also provide an interrupt each time the respective DMA buffer

pointer is incremented, which occurs whenever a new sample is read from and/or written to the DMA

buffer. This interrupt may be useful for triggering a read of the DMA pointer status value, which is the

actual 12-bit DMA address counter output. This value indicates exactly where the current address is

pointing to in the overall DMA buffer.

TMPR3911 Datasheet(PDF) 285 Page - Toshiba Semiconductor