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TMPR3911 Datasheet(PDF) 283 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 283 Page - Toshiba Semiconductor |
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283 / 462 page  Chapter 13 SIB Module 13-13 Table 13.3.4 SIB Holding and Shift Register Formats (Subframe 0) Subframe 0 Sound 16 Bit, Telecom 16 Bit: Frame SR[64:49] SR[48:33] SR[32:17] SR[16:1] 0 sndtxhold[31:16] sf0aux[31:18], VS, VT teltxhold[31:16] sf0aux[15:0] 1 sndtxhold[15:0] sf0aux[31:18], VS, VT teltxhold[15:0] sf0aux[15:0] 2 sndtxhold[31:16] sf0aux[31:18], VS, VT teltxhold[31:16] sf0aux[15:0] 3 sndtxhold[15:0] sf0aux[31:18], VS, VT teltxhold[15:0] sf0aux[15:0] Subframe 0 Sound 16 Bit, Telecom 8 Bit: Frame SR[64:49] SR[48:33] SR[32:17] SR[16:1] 0 sndtxhold[31:16] sf0aux[31:18], VS, VT teltxhold[31:24], 8b0sf0aux[15:0] 1 sndtxhold[15:0] sf0aux[31:18], VS, VT teltxhold[23:16], 8b0 sf0aux[15:0] 2 sndtxhold[31:16] sf0aux[31:18], VS, VT teltxhold[15:8], 8b0 sf0aux[15:0] 3 sndtxhold[15:0] sf0aux[31:18], VS, VT teltxhold[7:0], 8b0 sf0aux[15:0] Subframe 0 Sound 8 Bit, Telecom 16 Bit: Frame SR[64:49] SR[48:33] SR[32:17] SR[16:1] 0 sndtxhold[31:24], 8b0 sf0aux[31:18], VS, VT teltxhold[31:16] sf0aux[15:0] 1 sndtxhold[23:16], 8b0 sf0aux[31:18], VS, VT teltxhold[15:0] sf0aux[15:0] 2 sndtxhold[15:8], 8b0 sf0aux[31:18], VS, VT teltxhold[31:16] sf0aux[15:0] 3 sndtxhold[7:0], 8b0 sf0aux[31:18], VS, VT teltxhold[15:0] sf0aux[15:0] Subframe 0 Sound 8 Bit, Telecom 8 Bit: Frame SR[64:49] SR[48:33] SR[32:17] SR[16:1] 0 sndtxhold[31:24], 8b0 sf0aux[31:18], VS, VT teltxhold[31:24], 8b0 sf0aux[15:0] 1 sndtxhold[23:16], 8b0 sf0aux[31:18], VS, VT teltxhold[23:16], 8b0 sf0aux[15:0] 2 sndtxhold[15:8], 8b0 sf0aux[31:18], VS, VT teltxhold[15:8], 8b0 sf0aux[15:0] 3 sndtxhold[7:0], 8b0 sf0aux[31:18], VS, VT teltxhold[7:0], 8b0 sf0aux[15:0] NOTE: “VS” = valid sound flag bit; “VT” = valid telecom flag bit “8b0” = 8-bit field of zero values “SR” = Shift Register |
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