TMPR3911 datasheet(302/462 Pages) TOSHIBA

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Chapter 14 SPI Module

14-2

14.2 Description

14.2.1

Block Diagram

SPIOUT

Baud Rate

Generator

Data To CPU

SPIIN

16 Bit

Transmitter

Holding

Data From

CPU

16 Bit

Shift

16 Bit

Receiver

Holding

Inter

Character

Delay

Counter

Interrupt

Logic

Figure 14.2.1 SPI Block Diagram

The SPI Module primarily consists of a 16-bit Shift Register, a 16-bit Transmitter Holding Register, a

16-bit Receiver Holding Register, a Baud Rate Generator, an Inter Character Delay Counter, and

Interrupt Logic. A block diagram of the SPI Module is shown in Figure 14.2.1.

14.2.2

Baud Rate Generator

The rate of the SPICLK signal is determined by the value of the BAUDRATE[3:0] bits in the SPI

Control Register. The BAUDRATE[3:0] bits are used by the Baud Rate Generator to divide the SPI

master clock generated by the Clock Module logic. The typical frequency of the SPI master clock is

shown in the table below.

Table 14.2.1

SPI Master clock

frequency (fSPIMCLK)

Main System clock

frequency

Comment

TMPR3912AU-92/XB-92

9.216 MHz

46.080 MHz

fSYSCLK = 11.520 MHz,

RF[1:0] = 00, SLOWBUS = 0

TMPR3911BU/BXB

5.8982 MHz

29.4912 MHz

fSYSCLK = 7.3728 MHz,

RF[1:0] = 00, SLOWBUS = 0

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