TMPR3911 datasheet(298/462 Pages) TOSHIBA

298 / 462 page

Chapter 13 SIB Module

13-28

SNDBUFF1TIME:

The sound DMA controller supports two buffer addressing modes depending on the state of this

bit. When SNDBUFF1TIME is set to a logic “1”, the sound DMA controller will stop executing

when it reaches the end of the DMA buffer. When SNDBUFF1TIME is cleared to a logic “0”, the

sound DMA controller will loop back to the start of the DMA buffer when the end of the DMA

buffer is reached and will continue operating in a continuous and circular manner.

SNDDMALOOP:

The sound DMA controller supports two full-duplex loopback modes depending on the state of

this bit. When SNDDMALOOP is set to a logic “1”, the sound DMA controller issues RX DMA

requests first, followed by TX DMA requests. This ordering allows an RX-to-TX immediate

loopback via the DMA buffer. When SNDDMALOOP is cleared to a logic “0”, the sound DMA

controller issues TX DMA requests first, followed by RX DMA requests. This ordering allows a

single circular DMA buffer to be used for both TX and RX, if so desired.

SNDDMAPTR[13:2]:

read-only

These bits provide the status of the sound DMA counter.

ENDMARXSND:

This bit enables the sound DMA receive function. Setting this bit to a logic “1” enables the

DMA mode. Clearing this bit to a logic “0” disables the DMA mode. This bit should not be set

until the SNDRXSTART, SNDTXSTART, and SIBSIZE registers are setup and the SIB module is

enabled (ENSIB asserted) and ENSND is set. Either ENDMARXSND or ENDMATXSND or both

can be set at a time since the sound DMA controller can support full duplex operation.

ENDMATXSND:

This bit enables the sound DMA transmit function. Setting this bit to a logic “1” enables the

DMA mode. Clearing this bit to a logic “0” disables the DMA mode. This bit should not be set

until the SNDRXSTART, SNDTXSTART, and SIBSIZE registers are setup and the SIB module is

enabled (ENSIB asserted) and ENSND is set. Either ENDMARXSND or ENDMATXSND or both

can be set at a time since the sound DMA controller can support full duplex operation.

TELBUFF1TIME:

The telecom DMA controller supports two buffer addressing modes depending on the state of

this bit. When TELBUFF1TIME is set to a logic “1”, the telecom DMA controller will stop

executing when it reaches the end of the DMA buffer. When TELBUFF1TIME is cleared to a logic

“0”, the telecom DMA controller will loop back to the start of the DMA buffer when the end of the

DMA buffer is reached and will continue operating in a continuous and circular manner.

TELDMALOOP:

The telecom DMA controller supports two full-duplex loopback modes depending on the state

of this bit. When TELDMALOOP is set to a logic “1”, the telecom DMA controller issues RX

DMA requests first, followed by TX DMA requests. This ordering allows an RX-to-TX immediate

loopback via the DMA buffer. When TELDMALOOP is cleared to a logic “0”, the telecom DMA

controller issues TX DMA requests first, followed by RX DMA requests. This ordering allows a

single circular DMA buffer to be used for both TX and RX, if so desired.

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