TMPR3911 datasheet(294/462 Pages) TOSHIBA

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Chapter 13 SIB Module

13-24

ENSND:

This bit is used to enable/disable sound processing for this SIB module. Setting this bit to a logic

“1” enables sound processing. Clearing this bit to a logic “0” disables sound processing. This bit

should not be set until after the SIB module is setup, then ENSIB asserted.

Special timing restrictions are required whenever an enable/disable command is sent to

TC35143 and/or other external codec device (see Figure 13.3.3). First, after SIBSF0INT (if

SELSNDSF1

= “0”) or SIBSF1INT (if SELSNDSF1 = “1”) is asserted, the CPU then writes a

sound codec enable command to TC35143 via the SF0AUX (if SELSNDSF1

= “0”) or SF1AUX

(if SELSNDSF1

= “1”) register. The CPU then asserts ENSND. Both of these CPU transactions

must occur within the same SIB frame period, which is before the next SIBSF0INT (if

SELSNDSF1

= “0”) or SIBSF1INT (if SELSNDSF1 = “0”). This ensures that the sample rate

counters within the TMPR3911/12 and TC35143 are fully phase-synchronized.

SIBLOOP:

This bit is used for IC testing and should not be set. Setting this bit to a logic “1” will cause the

SIB serial transmitted data to be internally looped back to the SIB serial receive data path. The data

is inverted when this mode is selected. Setting this bit to a logic “0” selects the normal SIBDIN pin

as the SIB serial receive data source.

ENSF1:

This bit is used to enable/disable SIB subframe 1 processing. Setting this bit to a logic “1”

enables SIB subframe 1. Clearing this bit to a logic “0” disables SIB subframe 1, causing the SIB

serial transmitted data during this subframe to be zeroed and all received data during this subframe

to not be processed by the SIB module. This bit should be set before ENSIB is asserted.

ENSF0:

This bit is used to enable/disable SIB subframe 0 processing. Setting this bit to a logic “1”

enables SIB subframe 0. Clearing this bit to a logic “0” disables SIB subframe 0, causing the SIB

serial transmitted data during this subframe to be zeroed and all received data during this subframe

to not be processed by the SIB module. This bit should be set before ENSIB is asserted.

ENSIB:

This bit is used to enable/disable the SIB module. Setting this bit to a logic “1” enables the SIB

module. Clearing this bit to a logic “0” disables the SIB module and keeps the module in a reset

state but gives no effect on the SIB Control Register.

TMPR3911 Datasheet(PDF) 294 Page - Toshiba Semiconductor