TMPR3911 datasheet(293/462 Pages) TOSHIBA

293 / 462 page

Chapter 13 SIB Module

13-23

SND16:

This bit is used to configure the SIB sound input and output format as 8-bit versus 16-bit mode.

Setting this bit to a logic “1” selects 16-bit mode. Clearing this bit to a logic “0” selects 8-bit mode.

SNDFSDIV[6:0]:

These bits select the divider modulus for the 7-bit programmable counter used to generate the

sound sample rate clock, which is derived by dividing down an internal SIB clock of rate equal to

the 4 times the SIB frame rate or 2 times the SIB subframe rate (where each frame consists of 128

serial data bits). This programmable divider consists of a down-counter which counts down from

SNDFSDIV to zero, so the value loaded for SNDFSDIV should be the desired divider modulus

−1.

For example, if SIBMCLK

= 18.432 MHz and SIBSCLK = 9.216 MHz (= SIBMCLK ÷ 2), in

order to generate a sound sample rate of 24 kHz, the value loaded for SNDFSDIV should

= 11,

since 9.216 MHz

÷ (12 × 32) = 24 kHz.

SELTELSF1:

This bit is used to select between SIB subframe 0 and subframe 1 for the telecom data source

and destination. Setting this bit to a logic “1” selects SIB subframe 1 as the telecom source.

Clearing this bit to a logic “0” selects SIB subframe 0 as the telecom source.

SELSNDSF1:

This bit is used to select between SIB subframe 0 and subframe 1 for the sound data source and

destination. Setting this bit to a logic “1” selects SIB subframe 1 as the sound source. Clearing this

bit to a logic “0” selects SIB subframe 0 as the sound source.

ENTEL:

This bit is used to enable/disable telecom processing for the SIB module. Setting this bit to a

logic “1” enables telecom processing. Clearing this bit to a logic “0” disables telecom processing.

This bit should not be set until after the SIB module is setup, then ENSIB asserted.

Special timing restrictions are required whenever an enable/disable command is sent to

TC35143 and/or other external codec device (see Figure 13.3.3). First, after SIBSF0INT (if

SELTELSF1

= “0”) or SIBSF1INT (if SELTELSF1 = “1”) is asserted, the CPU then writes a

telecom codec enable command to TC35143 via the SF0AUX (if SELTELSF1

= “0”) or SF1AUX

(if SELTELSF1

= “1”) register. The CPU then asserts ENTEL. Both of these CPU transactions

must occur within the same SIB frame period, which is before the next SIBSF0INT (if

SELTELSF1

= “0”) or SIBSF1INT (if SELTELSF1 = “0”). This ensures that the sample rate

counters within the TMPR3911/12 and TC35143 are fully phase-synchronized.

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