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TMPR3911 Datasheet(PDF) 296 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 296 Page - Toshiba Semiconductor

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Chapter 13 SIB Module
13-26
13.6.10 SIB Telecom RX Holding Register
OFFSET
= $07C:
read-only
Bit
Label
RESET
Read/Write
31-0
TELRXHOLD[31:0]
–
R
TELRXHOLD[31:0]:
read-only
These bits represent the telecom data to be received. Telecom data can be either read directly
from this register by the CPU or transparently written to the telecom RX DMA buffer from this
register. This register should only be read by the CPU after the TELININT interrupt is set. The
sound and telecom data processing can be configured from among several possible formats (mono
versus stereo and 8-bit versus 16-bit data formats); see Table 13.3.4
∼13.3.7 for a summary of these
formats.
13.6.11 SIB Subframe 0 Control Register
OFFSET
= $080:
Bit
Label
RESET
Read/Write
31-0
SF0AUX[31:0]
X
R/W
SF0AUX[31:0]:
These bits represent the control data to be transmitted during SIB subframe 0. This register can
be loaded by the CPU asynchronously with respect to the SIB frame timing (although special
timing restrictions are required whenever an enable/disable command is sent to TC35143 and/or
other external codec device). Whenever this register is not updated, the previous contents are
transmitted during consecutive SIB frames.
13.6.12 SIB Subframe 1 Control Register
OFFSET
= $084:
Bit
Label
RESET
Read/Write
31-0
SF1AUX[31:0]
X
R/W
SF1AUX[31:0]:
These bits represent the control data to be transmitted during SIB subframe 1. This register can
be loaded by the CPU asynchronously with respect to the SIB frame timing (although special
timing restrictions are required whenever an enable/disable command is sent to TC35143 and/or
other external codec device). Whenever this register is not updated, the previous contents are
transmitted during consecutive SIB frames.



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