VNF1248F datasheet(44/79 Pages) STMICROELECTRONICS

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12.2

Signal description

Serial clock SCK

This input signal provides the timing of the serial interface. Data present at Serial Data Input (SDI) are latched on

the rising edge of Serial Clock (SCK). Data on Serial Data Output (SDO) change after the falling edge of Serial

Clock (SCK).

Serial data input SDI

This input signal is used to transfer data serially into the device. It receives data to be written. Values are sampled

on the rising edge of Serial Clock (SCK).

Serial data output SDO

This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of

Serial Clock (SCK).

Chip select CSN

The communication interface is deselected, when this input signal is logically high. A falling edge on CSN enables

and starts the communication while a rising edge finishes the communication and the sent command is executed

when a valid frame was sent. During communication start and stop the Serial Clock (SCK) has to be logically low.

12.3

SPI protocol

SDI format during each communication frame starts with a command byte. It begins with two bits of operating

code (OC1, OC0) which specify the type of operation (read, write, read and clear status, read device information)

and it is followed by a 6-bit address (A5:A0). The command byte is followed by three input data bytes: (D23:D16),

(D15:D8) and (D7:D0).

Table 34. Command byte

MSB

LSB

OC1

OC0

Table 35. Input data byte 1

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

Table 36. Input data byte 2

MSB

LSB

D15

D14

D13

D12

D11

D10

Table 37. Input data byte 3

MSB

LSB

Table 38. Global status byte

MSB

LSB

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SDO format during each communication frame starts with a specific byte called Global Status Byte (see GSB byte

for more details on bit0–bit7). This byte is followed by three output data bytes (D23:D16), (D15:D8) and (D7:D0).

VNF1248F

SPI functional description

DS14109 - Rev 7

page 44/79

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