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VNF1248F Datasheet(PDF) 57 Page - STMicroelectronics |
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VNF1248F Datasheet(HTML) 57 Page - STMicroelectronics |
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57 / 79 page  Table 55. SR#2: status register 2; address 12h Bit Default Name Description Access 23 0 Unused R 22÷17 0x0 NVM_FAIL Status of NVM download into RAM and internal registers bit = ‘1’ --> correspondent NVM row download failed (parity err.) bit = ‘0’ --> correspondent NVM row downloaded correctly R/C 16÷15 0x0 NVM_OP_STATUS NVM Read/Write operation status 00 --> IDLE: NVM operation not started 01 --> RUN: NVM operation started running 10 --> END: NVM operation completed successfully 11 --> ABORT: NVM operation aborted (wrong sector access) R/C 14÷2 0x000 CURR_SENSE 13-bit ADC conversion related to current sense amplifier, ranging from 0V to 160 mV; unidirectional current through an external sense resistor. R 1 0 UPDT_CURR Updated status bit. This bit is set when the value is updated and cleared when the register is read. R 0 1 Parity bit ODD parity bit check Table 56. SR#3: status register 3; address 13h Bit Default Name Description Access 23 Unused 22 ÷ 13 0000000000 TJ 10-bit ADC conversion related to TJ (device temperature) R 12 0 UPDT_TJ Updated status bit. This bit is set when the value is updated and cleared when the register is read. R 11 ÷ 2 0000000000 NTC 10-bit ADC conversion related to NTC (External MOSFET temperature sensing through an external NTC resistor) R 1 0 UPDT_NTC Updated status bit. This bit is set when the value is updated and cleared when the register is read. R 0 Parity bit ODD parity bit check Table 57. SR#4: status register 4; address 14h Bit Default Name Description Access 23 ÷ 12 Unused 22 ÷ 13 0000000000 VDS 10-bit ADC conversion of the voltage across the HS switch (VS-OUT). This register is not refreshed during VDS self-test execution. R 12 0 UPDT_VDS Updated status bit. This bit is set when the value is updated and cleared when the register is read. R 11 ÷ 2 0000000000 VOUT 10-bit ADC conversion of the OUT pin R 1 0 UPDT_VOUT Updated status bit. This bit is set when the value is updated and cleared when the register is read. R 0 Parity bit ODD parity bit check Table 58. SR#5: status register 5; address 15h Bit Default Name Description Access 23 ÷ 14 Unused 13 S_T_VDS_MAX1 This bit is set if VDS_THRS is reached during VDS self-test. R/C VNF1248F SPI functional description DS14109 - Rev 7 page 57/79 |
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