VNF1248F datasheet(47/79 Pages) STMICROELECTRONICS

47 / 79 page

12.8

SPI device information

Specific information can be read but not modified during this mode.

Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to

determine which information is read, whilst the other three data bytes are "don’t care".

Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the

serial clock (SCK). The first byte corresponds to the Global Status byte, second byte to the content of the

addressed register, third and forth bytes are 0x00.

Figure 18. SPI read device information

GADG1010171521PS

CSN

SDI

SDO

Global Status byte

MSB

LSB

Data byte

MSB

LSB

Command byte

MSB

Address

LSB

Don’t care

Read and clear status

operation

MSB

LSB

(8 bits)

(24 bits)

12.9

Special commands

0xFF - SWReset: sets all control registers to default and clears all status register

An Opcode ‘11’ (read device information) addressed at ‘111111’ forces a Software Reset of the device, second,

third and forth bytes are "don't care" provided that at least one bit is zero.

Note:

In the case of an OpCode '11' at address '111111' with data field equal to '1111111111111111' the SPI frame is

recognized as a frame error and SPIE bit of GSB is set.

Table 43. 0xFF: (SW_Reset)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Command

OC1

OC0

Address

DATA1

X(1)

DATA2

DATA3

1. X: do not care

0xBF - Clear all status registers (RAM access)

When an OpCode ‘10’ (read and clear operation) at address b’111111 is performed.

VNF1248F

SPI functional description

DS14109 - Rev 7

page 47/79

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