VNF1248F datasheet(4/79 Pages) STMICROELECTRONICS

4 / 79 page

Table 1. Pin functions

Pin #

Name

Function

TAB

GND

VSPI

DC supply input for the SPI interface. 3.3 V and 5 V are compatible.

CSN

Chip select (active low) for SPI communication. It is the selection pin of the device. CMOS compatible

input.

SDI

Serial data input for SPI communication. Data is transferred serially into the device and sampled on SCK

rising edge.

SDO

Serial data output for SPI communication. Data is transferred serially out of the device on the SCK falling

edge.

SCK

Serial clock for SPI communication. It is a CMOS compatible input.

DIAG

Open drain logic output. Diagnostic feedback. DIAG = '0' if ((SR1.FAILSAFE_ST='1' or

(CR1.AUTO_ON_DIS='1') and BYPASS_SAT='1') or (GSB.DIAGS = '1') or (GSB.DE = '1') or "internal

oscillator fault event" else '1'

TEST1

Test mode pin 1 - It must be connected to the ground through 1 kΩ resistor.

TEST2

Test mode pin 2 - It must be connected to the ground through 1 kΩ resistor.

DIN

Direct input to wake-up device from standby and to control directly gate turn-on/turn-off. If not used, must

be connected to the ground through 1 kΩ resistor.

HWLO

Active high input pin compatible with 3.3 V and 5 V CMOS. If not used, must be connected to the ground

through 1 kΩ resistor.

11, 16,

17, 22,

26, 32

N.C

Not connected.

V3V3

Output of the 3.3 V internal LDO voltage regulator (logic and I/O supply).

Connect a low ESR capacitor (1 μF) close to this pin.

GND

Ground connection.

EXT_LDO External V3V3 supply. If not used, must be connected to the ground through 1 kΩ resistor.

OUTST

Gate status monitor.

NTC_M

Negative input pin for external NTC resistor.

NTC

Positive input pin for external NTC resistor.

ISNS_N

Current sense amplifier negative input.

ISNS_P

Current sense amplifier positive input.

OUT

External FET source connection.

HS_GATE Output of the gate driver for the external FET.

Input supply pin. Connect to the 12 V, 24 V, 48 V battery voltage.

Charge pump output.

CP2P

Charge pump–Positive terminal of the flying capacitor CP2.

CP2M

Charge pump–Negative terminal of the flying capacitor CP2.

CP1P

Charge pump–Positive terminal of the flying capacitor CP1.

CP1M

Charge pump–Negative terminal of the flying capacitor CP1.

VNF1248F

Block diagram and pin description

DS14109 - Rev 7

page 4/79

VNF1248F Datasheet(PDF) 4 Page - STMicroelectronics

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