VNF1248F datasheet(72/79 Pages) STMICROELECTRONICS

72 / 79 page

Revision history

Table 67. Document revision history

Date

Revision

Changes

20-Dec-2022

Initial release.

07-Nov-2023

Updated Section Features on cover page.

Updated Section 1 Block diagram and pin description, Table 2. Absolute maximum rating,

Section 2.3 Main electrical characteristics, Figure 4. eFuse I2-t typical curve (VOC_thrs

minimum - VHSC_thrs maximum), Figure 5. eFuse I2-t typical curve (generic thresholds),

Figure 6. Current sense self-test flow sequence, Figure 8. External FET stuck-on self-test -

flow sequence for entry, Section 6 DIN input management, Section 9 Capacitive charging

mode - CCM, Section 10.1 NVM-Programmable default configuration, Table 45. RAM memory

map, Table 46. ROM memory map (ID12.2), Section 12.13 Control registers, Section 13

Functional description, Figure 23. Device functionalities status vs device states and Section

14 Application information.

Added Section 7 Bypass control management, Section 8 Ext LDO, Section 11.8 Current sense

under voltage (CS_UV) and Section 13.1 Operating modes, Section 5 VSPI_UV.

18-Mar-2024

Updated Figure 1. Block diagram, Table 4. Supply specification, Table 5. SPI logic inputs

(CSN, SCK, and SDI) specification, Table 20. Bypass switch, Section 6.4: Fail-safe state,

Section 6.2: Unlocked state, Table 6. SPI logic output (SDO) specification, Table 11. DIN logic

input pin specification, Table 12. OUTST logic output pin specification, Table 16. External FET

VDS protection, Table 28. External LDO voltage and current, Section 10.1.2: NVM default

configuration and RAM registers in fail-safe, Table 35. Current sense undervoltage thresholds

and Figure 21. Application diagram.

Added Section 6.3: Locked state, Section 9: Capacitive charging mode–CCM and Section

10.1.4: Default configuration upload to RAM.

Minor text changes.

02-Jul-2024

Updated Features on cover page.

Updated Table 1. Pin functions, Table 2. Absolute maximum rating, Table 4. Supply

specification, Table 5. SPI logic inputs (CSN, SCK, and SDI) specification, Table 7. SPI timing

specification, Figure 3. SPI specification: timing waveforms, Table 8. HWLO logic input pin

specification, Table 12. OUTST logic output pin specification, Table 14. External FET gate

driver specification, Table 15. Current sense amplifier , Table 17. External FET VDS

protection, Table 18. Hard short circuit protection with integrated 10-bit ADC,

Table 19. Overcurrent protection, and Table 22. VOUT A-to-D conversion.

Updated title of Table 11. Voltage and current thresholds of DIN PIN to Table 11. DIN logic

input pin specification, and Table 12. Voltage and current thresholds of OUTST PIN to

Table 12. OUTST logic output pin specification.

Updated Figure 7. Current sense self-test flow sequence, Figure 8. VDS monitor self-test flow

sequence, and Figure 9. External FET stuck-on self-test flow sequence for entry.

Updated Section 6.1: Standby state, replaced Figure 10. UNLOCKED state – DIN control

behavior with Table 24. Unlocked state - DIN control behavior, and Figure 11. FAILSAFE state

with Table 25. Fail-safe state. Removed Table 25. Voltage and current thresholds of DIN PIN.

Updated Table 26. Bypass switch control vs FSM.

Updated Section 9: Capacitive charging mode–CCM, Table 29. CCM PWM standard period

setting, Figure 10. CCM in unlocked state (1), and Figure 11. CCM in fail-safe state.

Updated Table 46. Global status byte - Bit description, Table 47. RAM memory map,

Table 49. CR#1: control register 1 (read/write); address 01h, Table 50. CR#2: control register

2 (read/write); address 02h , Table 51. CR#3: control register 3 (read/write); address 03h,

Table 52. CR#4: control register 4 (read/write); address 04h, Table 53. CR#5: control register

5 (read/write); address 05h, Table 49. CR#1: control register 1 (read/write); address 01h, and

removed Table 51. S_T_CFG self test selection.

Updated Figure 20. State diagram, Section 13.3: Standby state, Section 13.4: Fail-safe state,

Section 13.5: Unlocked state, Section 13.6: Locked state, and replaced Figure 23. Device

functionalities status vs device states with Table 62. Device functionalities status vs device

states.

Updated Section 14: Application information.

Minor text changes.

VNF1248F

DS14109 - Rev 7

page 72/79

VNF1248F Datasheet(PDF) 72 Page - STMicroelectronics

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