VNF1248F datasheet(21/79 Pages) STMICROELECTRONICS

21 / 79 page

Figure 7. Current sense self-test flow sequence

Current Sense

Self-test

Configuration

Current Sense

Self-test

Configuration

CR#1→ S_T_CFG = --1

CR#2→ OVC_THR = <user option>

CR#2 →HSC_THR = <user option>

SELF-TEST CONFIGURATION

Turn-on pull-down current generator to produce

additional voltage drop of 100mV on Current Sense

Amplifier inputs

A/D CONVERSIONS & DELTA MEASURES

Perform Current Sense SAR A/D conversions

Compute difference between self-test measures and

last user measure available in Status Register SR#8

Store data result, self-test status and fault emulation

check in Status Register SR#7

UNLOCKED STATE

SELF-TEST STATE

Current Sense

Self-test

Execution

Current Sense

Self-test

END

UNLOCKED STATE

S_T_START = 1

LOCKED

S_T_STOP = 1

WD Timeout

HWLO = 1

TS_T_ACTIVE time duration

00 = IDLE

01 = RUN

10 = END

11 = ABORT

SELF-TEST CLOSURE

Turn-off pull-down current generator to restore

normal drop on Current Sense Amplifier inputs

No Current Sense A/D conversions during this

timeframe

Parity

Status

OVC_ST

HSC_ST

TS_T_WAITtime duration

During TS_T_ACTIVE and TS_T_WAIT

timeframes, Fast and Slow

trip protections are

inhibited, whilst all other

protections are active

(Self-test aborted, state

transition after TS_T_WAIT

expiration)

(Self-test aborted,

state transition

after TS_T_WAIT

expiration)

TEST COMPLETED

TS_T_ACTIVE = 5 μs

TS_T_WAIT = 5 μs

ADC self-test result

4.2

External FET VDS detection self-test

The purpose of the external FET VDS detection self-test is to verify the proper behavior of the complete VDS

monitor chain (sense/process/detection), from the analog input to the digital output.

Starting from the unlocked state, the VDS detection self-test is activated through a dedicated SPI frame. The

duration of this test is defined by tS_T_ACTIVE + tS_T_WAIT (10 μs); first tS_T_ACTIVE period is intended to convert

the value of the voltage across the drain and source terminals of the external FET, while tS_T_WAIT period is

needed to bring back the analog circuitry to normal configuration.

VNF1248F

Self-test

DS14109 - Rev 7

page 21/79

VNF1248F Datasheet(PDF) 21 Page - STMicroelectronics

VNF1248F Datasheet(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL