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VNF1248F Datasheet(PDF) 8 Page - STMicroelectronics |
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VNF1248F Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 79 page ![]() Symbol Parameter Test conditions Min. Typ. Max. Unit V3V3 external capacitor 1 μF 1. See Table 51. CR#3: control register 3 (read/write); address 03h. 2. Measured in test mode with the charge pump off. Table 5. SPI logic inputs (CSN, SCK, and SDI) specification Symbol Parameter Test conditions Min. Typ. Max. Unit IIL Low level input current (SCK and SDI) VIL = 1.5 V 1.7 - 4 µA Low level input current (CSN) -2.9 - -2 µA IIH High level input current (SCK and SDI) VIH = 2.1 V -13 - -3 µA High level input current (CSN) -18 - -10 µA VIL Low level input voltage - - 1.5 V VIH High level input voltage 2.1 - - V VI_HYST Input hysteresis voltage - 0.4 - V Table 6. SPI logic output (SDO) specification Symbol Parameter Test conditions Min. Typ. Max. Unit VOL Low level output voltage - - 0.3 * VSPI V VOH High level output voltage 0.7 * VSPI - - V ISDO_Ilow Low level output current VSDO = 1 V, VSPI = 5 V 45 - 96 mA ISDO_Ihigh High level output current VSDO = 4 V, VSPI = 5 V 15 - 32 mA ILO Output leakage current -1 - 1 µA Table 7. SPI timing specification Symbol Parameter Test conditions Min. Typ. Max. Unit fSCK SPI clock frequency - - 8 MHz tHSCK SCK high time 55 - - ns tLSCK SCK low time 55 - - ns tHCSN CSN high time 1 - - μs tSCSN CSN setup time–CSN low before SCK rising edge 100 - - ns tSSCK SCK setup time–SCK low before CSN rising edge 100 - - ns tSSDI SDI setup time before SCK rising edge 25 - - ns tHSDI SDI hold time 20 - - ns tCSNQV CSN falling edge until SDO valid - - 70 ns tCSNQT CSN rising edge until SDO tristate - 220 - ns tSCKQV SCK falling edge until SDO valid - - 50 ns tRSDO SDO rise time - - 25 ns tFSDO SDO fall time - - 25 ns tWHCH CSN low timeout -10% 50 +10% ms tWDTB Watchdog toggle bit timeout WD_TIME configuration: 00 -10% 50 +10% ms 01 100 VNF1248F Electrical specification DS14109 - Rev 7 page 8/79 |
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