 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VNF1248F Datasheet(PDF) 63 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
VNF1248F Datasheet(HTML) 63 Page - STMicroelectronics |
|
|
63 / 79 page  • Unlocked state, if one of the following conditions is met: 1. Watchdog fail 2. SPI communication error detected 3. HWLO external pin set high if LOCKED_MODE_EN bit (CR#1) set to '0' 4. ‘EN’ bit set to ‘0’ by SPI frame, if LOCKED_MODE_EN bit (CR#1) set to '0' • Locked state, if watchdog fails or SPI communication errors are detected • Self-test state, if watchdog fails or HWLO pin is set high The device can leave the fail-safe state to: • Standby state (see above) • Unlocked state, by well-defined SPI frame sequence 13.5 Unlocked state In this state the device functionalities are fully operative and controllable by hardware and software: • External FET controllable by SPI interface or DIN (if enabled) • Internal bypass controllable by SPI interface • Channel protection is enabled according to external FET and bypass status • Device protections enabled • SPI interface active (watchdog monitoring enabled) • RAM registers fully accessible • CCM capacitive charging mode functionality is available if enabled by a dedicated control bit The unlocked state can be reached from • Standby and fail-safe states (refer to previous sections) • Locked state, by well-defined SPI frame sequence • Self-test state, at the end of self-test execution or if the SPI self-test stop command is received The device can leave this state to • Standby and fail-safe states (refer to previous sections) • Locked state, if one of the following conditions is met: • 1. HWLO external pin set high, if LOCKED_MODE_EN it (CR#1) set to '1' 2. 'EN' bit set to '0' by SPI frame, if LOCKED_MODE_EN bit (CR#1) set to '1' • Self-test state, if a specific self-test has been selected and its execution has been triggered 13.6 Locked state In this state the device configuration cannot be changed, while user still has software/hardware turn-on/off control of external FET and bypass switch: • External FET controllable by SPI interface combined with DIN input (if enabled) • Internal bypass controllable by SPI interface • Channel protection enabled according to external FET and bypass status • Device protections enabled • SPI interface active (watchdog monitoring enabled) • RAM registers fully accessible if NVM_DEF_CFG_EN = 1 (device configuration from NVM) otherwise locked • Capacitive load burst charging mode functionality available if enabled either by dedicated control bit The device can reach this state only from unlocked and leave it to standby, fail-safe, or unlocked as described previously in this document. VNF1248F Functional description DS14109 - Rev 7 page 63/79 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
