VNF1248F datasheet(20/79 Pages) STMICROELECTRONICS

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Self-test

The following sections describe how the device supports the execution of the in-application tests needed to verify

the proper behavior of the hardware diagnostic verification during product lifetime. Configuration, control, and

check for each of the tests is performed in close relationship with the microcontroller, through SPI interface

communication.

Activities related to self-test are possible in a specific device state (self-test) to distinguish it from operating modes

(standby, wake-up, unlocked, and locked modes), allowing to manage differently diagnostic faults according to the

hardware feature under test.

Self-test control interface

The initialization of the self-test sequence (selection of the self-test, start, and stop command) is done through the

control register 1 (CR#1). Results are accessible through the status register 5 (SR#5), status register 6 (SR#6)

and status register 7 (SR#7).

4.1

Current sense self-test

The purpose of the current sense self-test is to verify the proper behavior of the full current sense chain, from the

analog input to the digital output.

Starting from the unlocked state, the current sense self-test is activated through a dedicated SPI frame. The

duration of this test is defined by tS_T_ACTIVE + tS_T_WAIT (10 μs); first tS_T_ACTIVE period is intended for measure

and A/D conversion execution, while tS_T_WAIT period is needed to allow transients expiration.

Once the self-test is started, an internal current generator provides a current sink able to produce an additional

voltage drop of 100 mV at the input pin of the internal comparator.

The result of the self-test is the difference between this converted value and the value already stored in SR#8

(HSC field), corresponding to the normal measurement performed during operation; such result is stored in SR#7

together with the self-test status.

The transition from self-test state to unlocked state is automatically ensured after the test is completed (around 10

µs) or if the test is stopped through S_T_STOP = 1 (self-test aborted).

The transition from the self-test state to the locked state occurs in case of watchdog timeout or HWLO = 1 (self-

test aborted).

When the self-test is in execution if bypass and ext_fet are ON, this state is kept.

VNF1248F

Self-test

DS14109 - Rev 7

page 20/79

VNF1248F Datasheet(PDF) 20 Page - STMicroelectronics