VNF1248F datasheet(45/79 Pages) STMICROELECTRONICS

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Table 39. Output data byte 1

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

Table 40. Output data byte 2

MSB

LSB

D15

D14

D13

D12

D11

D10

Table 41. Output data byte 3

MSB

LSB

12.4

Operating code definition

The SPI interface features four different addressing modes which are listed in Table 42.

Table 42. Operating codes

OC1

OC0

Meaning

Write operation

Read operation

Read and clear status operation

Read device information

12.5

Write mode

The write mode of the device allows writing the content of the input data byte into the addressed register (see list

of the registers in Table 47. RAM memory map). The incoming datum is sampled on the rising edge of the serial

clock (SCK), MSB first.

During the same sequence, the outgoing datum is shifted out MSB first on the falling edge of the CSN pin and

subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the global status byte,

the second, third and forth bytes to the previous content of the addressed register. Unused bits are always read

as 0.

Figure 15. SPI write operation

SDI

SDO

CSN

MSB

Address

Command Byte

(8 bits)

Global Status Byte

MSB

LSB

MSB

(previous content of register)

Data

(24 bits)

Data

LSB

GADG1010171330PS

VNF1248F

SPI functional description

DS14109 - Rev 7

page 45/79

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