VNF1248F datasheet(56/79 Pages) STMICROELECTRONICS

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Bit

Default

Name

Description

Access

It is reset:

1. in Fail-safe state if FS_MODE = `00'/`01' AND DIN falling edge occur.

2. in Unlocked/Locked state if DIN_CTRL_EN = 1 AND DIN falling edge

occur.

BYPASS_SAT

Low current bypass desaturation shut-down: a desaturation shut down of the

low current bypass (BYPASS_SAT = 1) occurs if the VDS exceeds the preset

threshold when HS is in off-state and the bypass is in on-state.

When BYPASS_SAT = 1 external MOSFET is automatically commanded on,

independently on OUTCTL.

This bit is reset if a DIN rising edge occurs.

The low current bypass is re-armed via SPI.

This bit is also set to 1 correspondingly to the transition from wake-up to

unlocked mode.

R/C

FUSE_LATCH

Current vs time latch-off: an overcurrent shut down of the MOSFET

(FUSE_LATCH = 1) occurs when the current sense voltage exceeds the

preset threshold for longer than the preset time

(I2-t curve emulating a traditional fuse). When it happens, the bypass is

switched off as well. The MOSFET is rearmed via SPI.

It is reset:

1. in Fail-safe state if FS_MODE = `00'/`01' AND DIN falling edge occur.

2. in Unlocked/Locked state if DIN_CTRL_EN = 1 AND DIN falling edge

occur.

R/C

OVC

Overcurrent warning: an overcurrent warning (OVC = 1) occurs even when the

current sense voltage exceeds the preset threshold for a time not longer than

the preset time.

This is a “real-time” bit.

DEV_OVT

Overtemperature shut-down (“real-time” bit). When it is set to 1, the high side,

bypass, and charge pump are switched off.

NTC_OVT

External MOS overtemperature: this bit is set when NTC is lower than

NTC_THR for more than a certain deglitch time. When it happens, the bypass

is switched off as well.

The MOSFET is rearmed via SPI.

It is reset:

1. in Fail-safe state if FS_MODE = `00'/`01' AND DIN falling edge occur.

2. in Unlocked/Locked state if DIN_CTRL_EN = 1 AND DIN falling edge

occur.

R/C

VGS_LOW

This bit is set in on-state when VGS falls below VGS_UVLO_*V for more than

VG_UVLO_DEGLITCH time (8us typ). When this bit is set, the external FET is

switched off.

It is reset:

1. in Fail-safe state if FS_MODE = `00'/`01' AND DIN falling edge occur.

2. in Unlocked/Locked state if DIN_CTRL_EN = 1 AND DIN falling edge

occur.

R/C

CP_LOW

This bit is set when VCP falls below VCP_low threshold (VS + 5 V) for more

than tCP_RISE (60us typ). When this bit is set, the external FET driver is

disabled. This is a “real-time” bit.

WD_FAIL

Watchdog failure bit:

[0]: watchdog OK;

[1]: watchdog failure in unlocked/locked/self-test state

When this bit is set, the device moves to the fail-safe state.

R/C

Parity bit

ODD parity bit check

VNF1248F

SPI functional description

DS14109 - Rev 7

page 56/79

VNF1248F Datasheet(PDF) 56 Page - STMicroelectronics

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