VNF1248F datasheet(61/79 Pages) STMICROELECTRONICS

61 / 79 page

Functional description

This functionality is managed by the 6-states based FSM, to distinguish between initial phase, after power-on

reset, low power status, active status (user full control), locked status (user output control, device configuration

locked), safe (limp-home) status, and autodiagnostic phase. Main control supports three different wake-up

sources from low power state and automatic FET turn-on (active standby feature).

The device state diagram is shown in the next figure.

13.1

Operating modes

The device can operate in the following different modes:

•

Power-on mode

•

Standby mode

•

Fail-safe mode

•

Unlocked mode

•

Locked mode

•

Self-test mode

Figure 20. State diagram

Notes:

(**) Transition to unlocked sets 'EN' bit to 1.

(***) Transition to fail-safe resets 'EN' bit to 0.

tSTBY_OUT = 4 μs

tSTBY_IN = 80 ms

tS_T_WAIT = 5 μs

Unlocked

Output status per unlocked table

Bypass status per unlocked table

SPI active

‘EN’ = 1 (**)

IS = IS(ON)

(‘BYPASSCTL’ = 1 AND VS-VOUT > VDS_bypass_sat)

((DIN = 1 for t > tSTBY_OUT) AND

(‘FS_MODE’ != 01))

(DIN = 0 AND CSN = 1 for t > tSTBY_IN)

AND ‘FS_MODE’ = 00

AND ‘BYPASS_SAT’ = 0

Fail-safe

Output status per fail-safe table

Bypass status per fail-safe table

DIAG status per fail-safe table

SPI is active

Control register locked

‘FAILSAFE_STATE’ = 1

‘EN’ = 0 (***)

Standby

Bypass = ‘BYPASSCTL’

Output OFF

SPI not active

RAM Registers at last state

‘GOSTBY’ = 0

ISPI = ISPI_STBY

IS = IS_Q

Locked

Output status per locked table

Bypass status per locked table

NVM or RAM locked configuration

SPI active

‘LOCKED_STATE’=1

‘EN’= 0

Power-on

Output OFF

Bypass OFF

RAM Registers default cfg

SPI not active

‘RSTB’ = 1

‘LOCKED_MODE_EN’ = 1 AND

(‘HWLO_ST’ = 1 OR ‘EN’ = 0)

‘WD_FAIL’ = 1 OR ‘GSB.SPIE’ = 1

‘WD_FAIL’ = 1 OR ‘GSB.SPIE’ = 1 OR

((‘LOCKED_MODE_EN’ = 0‘) AND

(HWLO_ST’ = 1 OR ‘EN’ = 0))

PoR

Reset

‘GoToUnlocked’ SPI Sequence

t > tPWON

Self-test

Output/Bypass status depending

on test

SPI active

‘EN’ = 1

‘S_T_START’ = 1 AND

‘S_T_CFG’ ≠ 000

Self-test completed OR

‘S_T_STOP’ = 1 after tS_T_WAIT

‘GoToUnlocked’

SPI Sequence

(to fail-safe):

‘WD_FAIL’ = 1 after tS_T_WAIT OR

‘HWLO_ST’ = 1 after tS_T_WAIT

(from self-test)

(to standby):

‘’GoToStandby’ SPI Sequence

(from locked)

all states

VS < VS_POR_OFF

VS > VS_POR_ON

(*) Transition to fail-safe sets 'BYPASS_SAT'status bit to 1 only if BYPASSCTL = 1 and VS-VOUT > VDS_bypass_sat .

VNF1248F

Functional description

DS14109 - Rev 7

page 61/79

VNF1248F Datasheet(PDF) 61 Page - STMicroelectronics

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