VNF1248F datasheet(78/79 Pages) STMICROELECTRONICS

78 / 79 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Configuration diagram (top through view) .................................................. 3

Figure 3.

SPI specification: timing waveforms...................................................... 9

Figure 4.

NTC bridge ..................................................................... 16

Figure 5.

eFuse I2-t typical curve (VOC_thrs minimum - VHSC_thrs maximum) ............................. 19

Figure 6.

eFuse I2-t typical curve (generic thresholds) ............................................... 19

Figure 7.

Current sense self-test flow sequence ................................................... 21

Figure 8.

VDS monitor self-test flow sequence .................................................... 23

Figure 9.

External FET stuck-on self-test flow sequence for entry ....................................... 24

Figure 10.

CCM in unlocked state (1)............................................................ 34

Figure 11.

CCM in fail-safe state .............................................................. 34

Figure 12.

NVM write operation ............................................................... 36

Figure 13.

NVM read operation ............................................................... 36

Figure 14.

SPI functional diagram.............................................................. 43

Figure 15.

SPI write operation ................................................................ 45

Figure 16.

SPI read operation ................................................................ 46

Figure 17.

SPI read and clear operation ......................................................... 46

Figure 18.

SPI read device information .......................................................... 47

Figure 19.

Timeout watchdog................................................................. 60

Figure 20.

State diagram.................................................................... 61

Figure 21.

Application diagram (MCU 3.3 V) ...................................................... 65

Figure 22.

Application diagram (MCU 5 V)........................................................ 65

Figure 23.

QFN32L Epad (5.0x5.0x1.0 mm) package outline ........................................... 67

Figure 24.

QFN32L Epad 5x5 mm carrier tape ..................................................... 69

Figure 25.

QFN32L Epad 5x5 marking information .................................................. 70

VNF1248F

List of figures

DS14109 - Rev 7

page 78/79

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