VNF1248F datasheet(62/79 Pages) STMICROELECTRONICS

62 / 79 page

13.2

Power-on state

The power-on state is the device reset state at power-on-reset and device startup.

•

As soon as the internal oscillator is ready, nonvolatile memory content is downloaded into the

corresponding RAM registers

•

External MOSFET and internal bypass are kept OFF

•

The SPI interface is not active

•

SPI global status byte RSTB bit is set to 1 to notify PoR event occurrence

•

Transition to the standby state is automatically triggered after the end of the NVM download phase

13.3

Standby state

In the standby state, the device is in quiescent power consumption and operates under the following conditions:

•

External FET off with all related internal power circuitry (charge pump)

•

Internal oscillator turned off, with registers frozen to last values before standby entry (powered without

clock)

•

Low current bypass can be ON or OFF according to the ‘BYPASS_CTL’ control bit/BYPASS_CTL_DEF

NVM bit

•

Protections are disabled apart bypass VDS monitoring, in case the bypass is in ON state, to detect

saturation and consequently wake-up the device

•

SPI interface is not active (watchdog monitor disabled)

•

DIAG pin kept high, unless device internal malfunction (NVM download failure after power-on)

The device can reach this state (standby entry) from:

•

Power-on state, after NVM download completion

•

Unlocked or locked state, through a well-defined SPI frame sequence

•

Fail-safe state (with FS_MODE = 00 configuration), if BYPASS_SAT=0 (no bypass fault) and DIN=0 for t >

tSTBY_IN, without any activity on the SPI interface during this interval.

The device can leave this state (wake-up) to:

•

Unlocked state, if CSN pin is kept low (by direct CSN control of SPI frame) for t > tSTANDBY_OUT

•

Fail-safe state, if one of the following conditions is met:

1. Internal bypass ON and bypass saturation detected (VS - VOUT > VDS_BYBASS_SAT)

2. DIN pin set to 1 for t > tSTANDBY_OUT, with FS_MODE configurations 00/10/11 (with configuration 01,

the device remains in standby)

13.4

Fail-safe state

In this state the device is in a safe operating mode, with limitations on software control and the following

properties:

•

External FET can be automatically turned-on (due to bypass fault during active standby) or DIN-controlled/

driven off/maintained with last unlocked status, depending on selected configuration (FS_MODE control

•

Bypass can be driven with NVM default/driven off/maintained with last unlocked status, depending on the

selected configuration (FS_MODE)

•

Channel protections enabled according to external FET and bypass status

•

Device protections enabled

•

The SPI interface is active

•

RAM control registers can be written but modifications are not effective or can be only readable (with some

exceptions detailed below), depending on device configuration (FS_DEF_CFG_EN control register field)

•

Capacitive load burst charging mode functionality is available if enabled by proper DIN toggling sequence

•

Watchdog monitor disabled

The fail-safe state can be reached from:

•

Standby state (see above)

VNF1248F

Functional description

DS14109 - Rev 7

page 62/79

VNF1248F Datasheet(PDF) 62 Page - STMicroelectronics

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