VNF1248F datasheet(35/79 Pages) STMICROELECTRONICS

35 / 79 page

Non-volatile memory (NVM) customer programming

The control logic unit enables the capability to program, by the user, part of the NVM memory embedded in the

device, to test and store the specific settings for some of the key parameters, to be used during the operations.

Specifically, one sector (sector 5) of the six available can be write/read by the customer, after having entered a

proper command sequence, needed to ensure a secure and safe access to this functionality, avoiding unexpected

write operations could corrupt NVM content.

To perform write/read operations, digital control exploits RAM register fields dedicated to the mentioned

parameters as source (for write) or destination (for read) of NVM data to be stored, or read; a specific logic map

memory; opposite mapping is performed by the same logic during read operation.

User access to NVM Write/Read functionalities is enabled by the following sequence:

1. SPI write frame to set UNLOCK bit to 1 (CR#3)

2. SPI write frame to write customer access key (CR#4)

The above steps shall be performed sequentially, not interleaved by any other command, otherwise user access

is not unlocked.

After having properly completed the sequence, register CR#4 makes available the following fields to control NVM

Write/Read operations:

•

NVM_ADDR: address of the NVM sector to be read/written

•

NVM_WR_EN: NVM operation type (1 --> write, 0 --> read)

•

NVM_OP_START: trigger bit to start the selected NVM operation

The steps for Programming/Write execution are the following:

1. The user writes through SPI those RAM registers fields related to parameters target of NVM programming

2. The user writes through SPI the required 2-steps access sequence

3. The user writes through SPI sector address, access type and start command in the unlocked dedicated

4. Digital control logic maps RAM register fields into the equivalent NVM sector

5. Digital control logic provides control, address, and data to NVM interface IP

6. NVM IP interface handles NVM memory IP programming procedure

7. NVM IP interface notifies programming phase completion to digital logic

8. User reads (and clear) through SPI RAM register field reporting NVM operation status

Note:

During NVM write execution, correspondent RAM register fields shall be kept constant, considering they are

direct sources of data stored into the NVM sector (no intermediate buffering).

In case of the customer NVM write involving only a subset of allowed programmable parameters (partial write), it

is mandatory to run first an NVM read operation, to fill the RAM register fields of those parameters that is not be

affected by the changes, avoiding overwriting their NVM locations with unwanted values (NVM write operation

consider all RAM register fields belonging to NVM target sector).

VNF1248F

Non-volatile memory (NVM) customer programming

DS14109 - Rev 7

page 35/79

VNF1248F Datasheet(PDF) 35 Page - STMicroelectronics

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