VNF1248F datasheet(76/79 Pages) STMICROELECTRONICS

76 / 79 page

List of tables

Table 1.

Pin functions ....................................................................... 4

Table 2.

Absolute maximum rating .............................................................. 5

Table 3.

Thermal data....................................................................... 6

Table 4.

Supply specification .................................................................. 6

Table 5.

SPI logic inputs (CSN, SCK, and SDI) specification ............................................ 8

Table 6.

SPI logic output (SDO) specification ....................................................... 8

Table 7.

SPI timing specification................................................................ 8

Table 8.

HWLO logic input pin specification ........................................................ 9

Table 9.

DIAG logic output pin specification ....................................................... 10

Table 10.

Device thermal shutdown ............................................................. 10

Table 11.

DIN logic input pin specification ......................................................... 10

Table 12.

OUTST logic output pin specification ..................................................... 10

Table 13.

Charge pump specification ............................................................ 10

Table 14.

External FET gate driver specification..................................................... 11

Table 15.

Current sense amplifier .............................................................. 11

Table 16.

Integrated VSENSE 13-bit ADC ......................................................... 11

Table 17.

External FET VDS protection........................................................... 12

Table 18.

Hard short circuit protection with integrated 10-bit ADC......................................... 13

Table 19.

Overcurrent protection ............................................................... 14

Table 20.

External FET thermal shutdown via NTC input ............................................... 15

Table 21.

Bypass switch ..................................................................... 16

Table 22.

VOUT A-to-D conversion .............................................................. 16

Table 23.

Self-test timing..................................................................... 17

Table 24.

Unlocked state - DIN control behavior..................................................... 26

Table 25.

Fail-safe state ..................................................................... 27

Table 26.

Bypass switch control vs FSM .......................................................... 28

Table 27.

CCM PWM Ton setting ............................................................... 31

Table 28.

CCM PWM max. start pulses number setting ................................................ 32

Table 29.

CCM PWM standard period setting ...................................................... 33

Table 30.

NVM mapped configuration parameters ................................................... 37

Table 31.

Device and output configuration options ................................................... 38

Table 32.

Control register fields (not NVM mapped) .................................................. 39

Table 33.

Current sense undervoltage thresholds.................................................... 42

Table 34.

Command byte .................................................................... 44

Table 35.

Input data byte 1 ................................................................... 44

Table 36.

Input data byte 2 ................................................................... 44

Table 37.

Input data byte 3 ................................................................... 44

Table 38.

Global status byte .................................................................. 44

Table 39.

Output data byte 1 .................................................................. 45

Table 40.

Output data byte 2 .................................................................. 45

Table 41.

Output data byte 3 .................................................................. 45

Table 42.

Operating codes ................................................................... 45

Table 43.

0xFF: (SW_Reset) .................................................................. 47

Table 44.

Clear all status registers (RAM access).................................................... 48

Table 45.

Global status byte .................................................................. 48

Table 46.

Global status byte - Bit description ....................................................... 48

Table 47.

RAM memory map .................................................................. 49

Table 48.

ROM memory map.................................................................. 50

Table 49.

CR#1: control register 1 (read/write); address 01h ............................................ 51

Table 50.

CR#2: control register 2 (read/write); address 02h ............................................ 52

Table 51.

CR#3: control register 3 (read/write); address 03h ............................................ 53

Table 52.

CR#4: control register 4 (read/write); address 04h ............................................ 53

Table 53.

CR#5: control register 5 (read/write); address 05h ............................................ 54

VNF1248F

List of tables

DS14109 - Rev 7

page 76/79

VNF1248F Datasheet(PDF) 76 Page - STMicroelectronics

VNF1248F Datasheet(HTML) 76 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL