TAS2120 datasheet(44/113 Pages) TI2

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PVDD over voltage protection is based on the monitored PVDD voltage compared against a programmable

threshold which can be controlled using PVDD_OVLO_TH_SEL in the internal boost mode, and

PVDD_OVLO_TH_SEL_EXT in the external PVDD mode of operation. The PVDD Over voltage protection is

enabled by default and can be disabled by setting PVDD_OV_DET_DIS bit high.

Table 6-40. PVDD Over voltage protection threshold,

internal Boost mode

PVDD_OVLO_TH_SEL[1:0]

Configuration

Over voltage threshold is 13.5V

Over voltage threshold is 14V

Over voltage threshold is 15V

11 (default)

Over voltage threshold is 16V

6.4.8 Thermal Protection

TAS2120 has internal device junction temperature monitor which protects the device against over temperature.

When the internal temperature rises above the Over temperature threshold, the device automatically shuts down

and sets the Over temperature flag in the corresponding Interrupt registers. The device can automatically retry

to power up if OTE_RETRY bit is set high. When set high, the device attempts to re-power up after every

RETRY_WAIT_TIME setting (default 1.5 seconds of retry)

Along with over temperature protection, the device has thermal warning thresholds to allow for system

to raise interrupts or flags as the junction temperature is approaching the shutdown. There are four

thermal warning flags available at the internal temperature of 105C, 115C, 125C and 135C. Each thermal

warning flag can be independently set to control the Interrupt generation on the IRQZ pad. The minimum

temperature and the step size of the temperature warning flag can be programmed using the registers

THERMAL_WARN_MIN_TEMP[23:0] and THERMAL_WARN_TEMP_STEP[23:0]

The real time internal junction temperature is monitored are stored in the register TMP_CNV and can be read

using i2c commands.

6.4.9 Clocks and PLL

In TDM/I2S Mode, the device operates from SBCLK. Table 6-41 below shows the valid SBCLK frequencies for

each sample rate and SBCLK to FSYNC ratio. For 44.1kHz based clocking, the same table is applicable with the

associated ratio change between 48ksps to 44.1ksps.

While the sampling rate of 192kHz is supported, data is internally down-sampled to 96kHz. Therefore audio

content greater than 40kHz should not be applied to prevent aliasing. This additionally affects all processing

blocks like BOP and limiter which should use 96 kHz fs when accepting 192 kHz audio.

If the sample rate is properly configured via the SAMPLE_RATE_CFG bits, no additional configuration is

required as long as the SBCLK to FSYNC ratio is valid. The device automatically detects the input PCM

FSYNC and BCLK frequency and auto configures itself to playback audio signal. The detected clock rates

can be read using the read only registers FS_RATIO_DETECTED and FS_RATE_DETECTED. The device will

detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to

minimize audible artifacts.

Table 6-41. Supported SBCLK Frequencies (MHz) (48 kHz based sample rates)

Sample

Rate (kHz)

SBCLK to FSYNC Ratio

128

192

256

384

512

125

250

500

16 kHz

0.384

0.512

0.768

1.024

1.536

2.048

3.072

4.096

6.144

8.192

24 kHz

0.384

0.576

0.768

1.152

1.536

2.304

3.072

4.608

6.144

9.216

12.288

32 kHz

0.512

0.768

1.024

1.536

2.048

3.072

4.096

6.144

8.192

12.288 16.384

48 kHz

0.768

1.152

1.536

2.304

3.072

4.608

6.144

9.216

12.288 18.432 24.576

96 kHz

1.536

2.304

3.072

4.608

6.144

9.216

12.288 18.432 24.576

TAS2120

SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025

www.ti.com

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