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TAS2120 Datasheet(PDF) 63 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 113 page  Table 7-31. SAR_MONITOR_02 Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 RESERVED R 0h Reserved 7.1.31 SAR_MONITOR_03 Register (Address = 28h) [Reset = 00h] Return to the Summary Table. This register provides sensed VBAT Voltage. Table 7-32. SAR_MONITOR_03 Register Field Descriptions Bit Field Type Reset Description 7-0 PVDD_CNV_MSB[7:0] R 0h Returns the SAR ADC PVDD monitored voltage MSBs. 7.1.32 SAR_MONITOR_04 Register (Address = 29h) [Reset = 00h] Return to the Summary Table. This register provides sensed VBAT Voltage. Table 7-33. SAR_MONITOR_04 Register Field Descriptions Bit Field Type Reset Description 7-4 PVDD_CNV_LSB[3:0] R 0h Returns the SAR ADC PVDD monitored voltage LSBs. 3-0 RESERVED R 0h Reserved 7.1.33 SAR_MONITOR_06 Register (Address = 2Ah) [Reset = 00h] Return to the Summary Table. This register provides sensed temperature. Table 7-34. SAR_MONITOR_06 Register Field Descriptions Bit Field Type Reset Description 7-0 TMP_CNV[7:0] R 0h Returns the SAR ADC Temperature monitored data. 7.1.34 CLASSD_CFG_01 Register (Address = 31h) [Reset = 04h] Return to the Summary Table. This register configures the class-D amplifier. Table 7-35. CLASSD_CFG_01 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h Reserved 5-4 CLASSD_OUTPUT_EDG ERATE_CTRL[1:0] R/W 0h Edgerate programmability control. 0h = Class-D output edge rate of approximately 0.5 V/ns 1h = Class-D output edge rate of approximately 1 V/ns 2h = Reserved 3h = Class-D output edge rate of approximately 2 V/ns 3 CLASSD_HIZ_MODE R/W 0h Amp output state in Noise gate mode (0 = Not Hi-Z, 1 = Hi-Z) 0h = Disabled 1h = Enabled 2 RESERVED R/W 1h Reserved 1-0 RESERVED R 0h Reserved www.ti.com TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: TAS2120 |
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