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TAS2120 Datasheet(PDF) 9 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 113 page  TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRRPV DD_EXT PVDD power-supply rejection ratio PVDD + 200 mVpp, fripple = 217 Hz 119 dB PVDD + 200 mVpp, fripple = 1 kHz 115 dB PVDD + 200 mVpp, fripple = 20 kHz 91 dB PSRRVB AT_EXT VBAT power-supply rejection ratio VBAT + 200 mVpp, fripple = 217 Hz 118 dB VBAT + 200 mVpp, fripple = 1 kHz 116 dB VBAT + 200 mVpp, fripple = 20 kHz 102 dB PSRRVD D_EXT VDD power-supply rejection ratio VDD + 200 mVpp, fripple = 217 Hz 113 dB VDD + 200 mVpp, fripple = 1 kHz 113 dB VDD + 200 mVpp, fripple = 20 kHz 91 dB Boost Converter VBOOST_ RANGE Max Output Voltage programmability Range Programmable in steps of 66mV 5.5 14.75 V VBOOST_S TEP Class-H Output Voltage Step Size 33 mV VBOOST Output Boost Voltage IO = 0.1A. Average output value. VBOOST_MAX_CTRL = max value 14.9 V IBOOST_C L Peak Input Current Limit BST_ILIM = Max Setting 5.1 A IBOOST_C L Peak Input Current Limit BST_ILIM = Min Setting 1.5 A Peak Input Current Limit Programmable step size 39.1 mA Boost Converter 2S Mode of operation VBOOST_ RANGE Output Voltage Range Programmable in steps of 66mV 10 14.75 V VBOOST_S TEP Class-H Output Voltage Step Size 33 mV IBOOST_C L Peak Input Current Limit (I2C mode) Max Setting 5.1 A IBOOST_C L Peak Input Current Limit Min Setting 1.5 A TDM Serial Port PCM Sample Rates and FSYNC Input Frequency 16 192 kHz SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns RMS Jitter above 40 kHz that can be tolerated without performance degradation 5 ns SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles PCM Playback Characteristics to fs ≤ 48 kHz Fs Sample Rates 16 48 kHz Audio Channel Passband LPF Corner Ripple < pass-band ripple 0.454 fs Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.1 dB www.ti.com TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TAS2120 |
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