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TAS2120 Datasheet(PDF) 13 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 113 page  TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ (1) Errata: Additional 2mA to 3mA current consumption expected if IRQZ signal is pulled high. Read more details in section "what to do and what not to do". 5.6 Timing Requirements TA = 25 °C, VDD = IOVDD = 1.8 V (unless other wise noted) MIN NOM MAX UNIT I2C - Standard Mode fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW LOW period of the SCL clock 4.7 μs tHIGH HIGH period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 μs tSU;DAT Data set-up time 250 ns tr SDA and SCL rise time 1000 ns tf SDA and SCL fall time 300 ns tSU;STO Set-up time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs Cb Capacitive load for each bus line 400 pF I2C - Fast Mode fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW LOW period of the SCL clock 1.3 μs tHIGH HIGH period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 0.6 μs tHD;DAT Data hold time: For I2C bus devices 0 0.9 μs tSU;DAT Data set-up time 100 ns tr SDA and SCL rise time 20 + 0.1 × Cb 300 ns tf SDA and SCL fall time 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs Cb Capacitive load for each bus line 400 pF TDM Port fsbclk SBCLK Frequency range 0.384 24.576 MHz tH(SBCLK) SBCLK high period 0.35/fsbclk ns tL(SBCLK) SBCLK low period 0.35/fsbclk ns tSU(FSYNC) FSYNC setup time 8 ns www.ti.com TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TAS2120 |
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