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TAS2120 Datasheet(PDF) 7 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 113 page  TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BW Amplifier input signal Bandwidth fs ≥ 96ksps, Gain error < Pass-Band Ripple 40 kHz VFS Full scale equivalent Voltage Measured at -6dBFS Input, Gain = 6dBV (Receiver Mode) 2.00 VRMS AGAIN Audio channel Gain programmability range Gain programmability in steps of 0.5dB 0 21 dBV AGAIN_ER R Amplifier Gain error POUT = 1W ±0.1 dB POUT = 0.25W, Gain = 6dBV (Receiver Mode) ±0.1 dB VOS Output Offset Voltage Idle channel –1 1 mV Idle channel, Gain = 6dBV (Receiver Mode) –1 1 mV FPWM Class-D PWM switching Frequency Average clock frequency 384 kHz PSRRVB AT VBAT power-supply rejection ratio VBAT + 200 mVpp, fripple = 217 Hz 118 dB VBAT + 200 mVpp, fripple = 1 kHz 115 dB VBAT + 200 mVpp, fripple = 20 kHz 80 dB PSRRVD D VDD power-supply rejection ratio VDD + 200 mVpp, fripple = 217 Hz 113 dB VDD + 200 mVpp, fripple = 1 kHz 113 dB VDD + 200 mVpp, fripple = 20 kHz 91 dB MUTE_A TTN Mute Attenuation Device is MUTE mode. DAC modulator running 113 dB AMPLIFIER PERFORMANCE - INTERNAL BOOST 2S Mode POUT_BO OST_2S Maximum Output Power - 1% THD+N RL = 8 Ω + 33 µH 10.0 W RL = 4 Ω + 33 µH 12.8 W RL = 8 Ω + 33 µH, VBAT2S = 8.4V 10.4 W RL = 4 Ω + 33 µH, VBAT2S = 8.4V 14.5 W POUT_BO OST_2S Maximum Output Power - 10% THD+N RL = 8 Ω + 33 µH, VBAT2S = 8.4V 12.6 W RL = 4 Ω + 33 µH, VBAT2S = 8.4V 17.5 W ηSYSTEM_ 1W_2S System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 89.9 % RL = 8 Ω + 33 µH, VBAT2S = 8.4V 89.5 % RL = 4 Ω + 33 µH 86.2 % RL = 4 Ω + 33 µH, VBAT2S = 8.4V 85.8 % ηSYSTEM_ MAX_POUT _2S System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 85 % RL = 8 Ω + 33 µH, VBAT2S= 8.4V 86.5 % RL = 4 Ω + 33 µH 77.4 % RL = 4 Ω + 33 µH, VBAT2S = 8.4V 78.0 % VN_2S Idle channel Noise A-Weighted, Gain = 6dBV (Receiver Mode), DAC-Running 7.0 µV A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.4 µV DNR_2S Dynamic Range A-Weighted, -60 dBFS Method, Gain = 6dBV (Receiver Mode) 108.9 dB A-Weighted, -60 dBFS Method, Gain = 21dBV (Speaker Mode) 114.4 dB www.ti.com TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TAS2120 |
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