TAS2120 datasheet(10/113 Pages) TI2

10 / 113 page

TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V,

IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S

Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate

disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to

20kHz un-weighted bandwidth (unless otherwise noted).(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Channel Stop Band Attenuation

≥ 0.55 fs

≥ 1 fs

Audio Channel Group Delay

Fin = 1kHz, Lowest latency mode (Y-

bridge, Class-H, Noise Gate disabled)

8.5

1/fs

Fin = 1kHz, Class-H disabled

16.5

1/fs

Fin = 1kHz, Class-H enabled

31.5

1/fs

DC to 20kHz, Lowest latency mode (HPF

bypassed, Y-bridge, Class-H, Noise Gate

disabled)

1/fs

DC to 20kHz, HPF bypassed, Class-H

disabled

1/fs

DC to 20kHz, HPF bypassed, Class-H

enabled

1/fs

PCM Playback Characteristics to fs > 48 kHz

Sample Rates

88.2

192

kHz

Audio Channel Passband LPF Corner

fs = 96 kHz

0.469

fs = 192 kHz

0.234

Audio Channel Passband Ripple

20 Hz to LPF cutoff

± 0.2

Audio Channel Stop Band Attenuation

fs = 96 kHz, fin ≥ 0.55 fs

fs = 96 kHz, fin ≥ 1 fs

fs = 192 kHz, 0.55 fs ≥ fin ≥ 0.275 fs

Audio Channel Group Delay

Fin = 1kHz, Fs = 96kHz, Lowest latency

mode (Y-bridge, Class-H, Noise Gate

disabled)

1/fs

Fin = 1kHz, Fs = 96kHz, Class-H disabled

6.7

1/fs

Fin = 1kHz, Fs = 96kHz, Class-H enabled

56.7

1/fs

DC to 20kHz, Fs = 96kHz, Lowest latency

mode (HPF bypassed, Y-bridge, Class-H,

Noise Gate disabled)

11.5

1/fs

DC to 40kHz, Fs=96kHz, HPF bypassed,

Class-H disabled

28.6

1/fs

DC to 40kHz, Fs=192 kHz, HPF

bypassed, Class-H enabled

117.8

1/fs

Protection Circuits

Thermal shutdown temperature

140

°C

Thermal shutdown retry time

1.5

VBAT undervoltage lockout threshold

(UVLO)

UVLO is asserted

1.9

UVLO is released

2.3

VDD undervoltage lockout threshold

(UVLO)

UVLO is asserted

1.4

UVLO is released

1.6

PVDD undervoltage lockout threshold

(UVLO)

UVLO is asserted, external PVDD mode

only

2.6

UVLO is released, external PVDD mode

only

2.8

PVDD overvoltage lockout threshold

(OVLO)

OVLO is asserted, OVLO protection

enabled.

TAS2120

SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025

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