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TAS2120 Datasheet(PDF) 12 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 113 page  TA = 25°C, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V ( External PVDD mode enabled), VDD = 1.8V, IOVDD = 1.8V, RL = 8Ω + 33µH, LBOOST(1S Boost mode) = 1µH, Fin = 1kHz, Fs = 48kHz, Gain = 21dBV, BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost, HW mode) = 4.1A, BST_ILIM (2S Boost, I2C mode) = 5.1A, SDZ=1, Noise gate disabled, Class-D edge rate set to 2V/ns, I2C mode of operation, Measured filter free with an Audio Precision using 22Hz to 20kHz un-weighted bandwidth (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ_IDLE Current consumption in Idle Channel VBAT, POUT = 0, Noise gate disabled 0.5 mA VBAT2S, POUT = 0, Noise gate disabled 0.35 mA VDD, POUT = 0, Noise gate disabled 6 mA IOVDD, POUT = 0, Noise gate disabled 0.1 mA Total Power, POUT = 0, Noise gate disabled 15.1 mW Current Consumption - External PVDD Mode (1) IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 0.1 uA VBAT, SDZ=0 0.1 uA VDD, SDZ=0 0.2 uA IOVDD, SDZ=0 0.1 uA IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 0.1 uA VBAT, All clocks Stopped 0.1 uA VDD, All clocks Stopped 12 uA IOVDD, All clocks Stopped 0.1 uA IQ_NG Current consumption in Idle channel PVDD, POUT = 0, Noise gate enabled 0.1 mA VBAT, POUT = 0, Noise gate enabled 0.15 mA VDD, POUT = 0, Noise gate enabled 2.2 mA IOVDD, POUT = 0, Noise gate enabled 0.1 mA Total Power, POUT = 0, Noise gate enabled 5.3 mW IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA VBAT, POUT = 0, Noise gate disabled 0.5 mA VDD, POUT = 0, Noise gate disabled 6 mA IOVDD, POUT = 0, Noise gate disabled 0.1 mA Total Power, POUT = 0, Noise gate disabled 14.7 mW DIGITAL IOs VIH High-level digital input logic voltage threshold All digital pins 0.7 x IOVDD V VIL Low-level digital input logic voltage threshold All digital pins 0.3 x IOVDD V VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD - 0.2 V V VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2 x IOVDD V VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V IIH (1) Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA IIL (1) Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA CIN Input capacitance for digital inputs All digital pins 5 pF TAS2120 SLASFC6A – AUGUST 2024 – REVISED AUGUST 2025 www.ti.com 12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TAS2120 |
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